Patents by Inventor Andreas Laschek-Enders
Andreas Laschek-Enders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9912331Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.Type: GrantFiled: August 25, 2017Date of Patent: March 6, 2018Assignee: IXYS CorporationInventor: Andreas Laschek-Enders
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Publication number: 20170373682Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.Type: ApplicationFiled: August 25, 2017Publication date: December 28, 2017Inventor: Andreas Laschek-Enders
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Patent number: 9813055Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.Type: GrantFiled: April 1, 2016Date of Patent: November 7, 2017Assignee: IXYS CorporationInventor: Andreas Laschek-Enders
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Publication number: 20170288661Abstract: A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventor: Andreas Laschek-Enders
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Patent number: 9210818Abstract: A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.Type: GrantFiled: March 24, 2015Date of Patent: December 8, 2015Assignee: IXYS Semiconductor GmbHInventors: Olaf Zschieschang, Andreas Laschek-Enders
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Patent number: 9129824Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.Type: GrantFiled: August 3, 2014Date of Patent: September 8, 2015Assignee: IXYS CorporationInventor: Andreas Laschek-Enders
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Publication number: 20150195928Abstract: A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.Type: ApplicationFiled: March 24, 2015Publication date: July 9, 2015Inventors: Olaf Zschieschang, Andreas Laschek-Enders
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Patent number: 9042103Abstract: A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.Type: GrantFiled: May 16, 2012Date of Patent: May 26, 2015Assignee: IXYS Semiconductor GmbHInventors: Olaf Zschieschang, Andreas Laschek-Enders
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Publication number: 20140342509Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.Type: ApplicationFiled: August 3, 2014Publication date: November 20, 2014Inventor: Andreas Laschek-Enders
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Patent number: 8847328Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.Type: GrantFiled: March 8, 2013Date of Patent: September 30, 2014Assignee: IXYS CorporationInventor: Andreas Laschek-Enders
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Publication number: 20140252410Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: IXYS CorporationInventor: Andreas Laschek-Enders
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Publication number: 20130021759Abstract: A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.Type: ApplicationFiled: May 16, 2012Publication date: January 24, 2013Applicant: IXYS Semiconductor GmbHInventors: Olaf Zschieschang, Andreas Laschek-Enders
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Patent number: 7780469Abstract: An arrangement between a power semiconductor module and a printed circuit board is disclosed, A printed circuit board includes strip conductors, and a power semiconductor module includes a module housing and power terminals. The power terminals extend to the exterior of the module housing and into contact with the strip conductors. A heat sink is disposed on a side of the power semiconductor module opposite the circuit board. A deformable means is disposed between the module housing and the circuit board and is configured to relieve a contact pressure load on the power terminals. A contact-pressure element is disposed on a side of the circuit board opposite the power semiconductor module. The contact-pressure element is integral with a first housing part of an arrangement housing, and the heat sink is integral with a second housing part of the arrangement housing. The two housing parts enclose the circuit board.Type: GrantFiled: March 26, 2008Date of Patent: August 24, 2010Assignee: IXYS CH GmbHInventors: Olaf Zschieschang, Andreas Laschek-Enders
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Publication number: 20080293261Abstract: An arrangement between a power semiconductor module and a printed circuit board is disclosed, A printed circuit board includes strip conductors, and a power semiconductor module includes a module housing and power terminals. The power terminals extend to the exterior of the module housing and into contact with the strip conductors. A heat sink is disposed on a side of the power semiconductor module opposite the circuit board. A deformable means is disposed between the module housing and the circuit board and is configured to relieve a contact pressure load on the power terminals. A contact-pressure element is disposed on a side of the circuit board opposite the power semiconductor module. The contact-pressure element is integral with a first housing part of an arrangement housing, and the heat sink is integral with a second housing part of the arrangement housing. The two housing parts enclose the circuit board.Type: ApplicationFiled: March 26, 2008Publication date: November 27, 2008Applicant: IXYS Seminconductor GmbHInventors: Olaf Zschieschang, Andreas Laschek-Enders