Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance.

Abstract: The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance.

Abstract: A compensating circuit for a mixer stage is provided, wherein the mixer stage has an input stage to which an input signal for mixing can be applied and has, following the input stage, a switching stage for mixing a differential input signal—obtained from the input stage as a function of the input signal—with an oscillator signal, wherein the input of the compensating circuit can be connected to an input signal terminal of the input stage and the output of the compensating circuit can be connected to an input signal terminal of the switching circuit at which the differential input signal obtained by means of the input stage is present, and wherein a compensating signal obtained by means of a compensating stage of the compensating circuit, in particular for compensating intermodulation products, can be produced by the compensating circuit at its output.

Abstract: An inverting stage is coupled between a single-ended in-put node and a first differential output node, and a non-inverting stage is coupled between the single-ended input node and a second differential output node. The inverting stage includes at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the first differential output node and the control terminal being coupled to a single-ended input node. The non-inverting stage includes at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second terminal being coupled to the single-ended input node. A bias current of the inverting stage is larger than a bias current of the non-inverting stage.

Abstract: An inverting stage is coupled between a single-ended in-put node and a first differential output node, and a non-inverting stage is coupled between the single-ended input node and a second differential output node. The inverting stage includes at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the first differential output node and the control terminal being coupled to a single-ended input node. The non-inverting stage includes at least one transistor with a first current terminal, a second current terminal, and a control terminal, the first current terminal being coupled to the second differential output node, and the second terminal being coupled to the single-ended input node. A bias current of the inverting stage is larger than a bias current of the non-inverting stage.

Abstract: A mixer stage is provided that includes an oscillator, a first input, a second input, a first output, a second output, a set of four controllable amplifier elements, and a first current source. The mixer stage further includes at least one second current source in addition to the first current source, the first current source and the at least one second current source can each be switched on and off by an associated switching input that is connected to an associated oscillator output. Pairs of amplifier elements of the set of four together with at least one of the at least two current sources in its switched-on state form a differential amplifier for an input signal present at the first input and the second input. A method for mixing frequencies is also provided.

Abstract: A method is presented for changing a frequency of a first local oscillator in a receiving system, which has a first receiver with the first local oscillator and a first frequency control element and a second receiver with a second local oscillator and a second frequency control element. The method is characterized in that the following steps are performed during a change in a frequency of the first local oscillator from an actual frequency of the first local oscillator to a target frequency, at which an actual frequency of the second local oscillator lies between the actual frequency of the first local oscillator and the target frequency: turning off the first local oscillator, control of the first frequency control element such that the first frequency control element provides a first base value, assigned to the target frequency, of a frequency control variable, turning on the first local oscillator, and setting of the frequency of the first local oscillator to the target frequency.

Abstract: A compensating circuit for a mixer stage is provided, wherein the mixer stage has an input stage to which an input signal for mixing can be applied and has, following the input stage, a switching stage for mixing a differential input signal—obtained from the input stage as a function of the input signal—with an oscillator signal, wherein the input of the compensating circuit can be connected to an input signal terminal of the input stage and the output of the compensating circuit can be connected to an input signal terminal of the switching circuit at which the differential input signal obtained by means of the input stage is present, and wherein a compensating signal obtained by means of a compensating stage of the compensating circuit, in particular for compensating intermodulation products, can be produced by the compensating circuit at its output.

Abstract: A mixer stage is provided that mixes a differential input signal with a differential square-wave signal of an oscillator, having a first amplifier element and a second amplifier element, each of which amplifier elements has a first current connection, a second current connection, and a connection for the differential input signal, having four control elements and also a first output and a second output, wherein the four control elements are modulated in pairs by the differential square-wave signal, thereby connecting each second current connection alternately, and in each case individually, to one of the two outputs. The mixer stage has field-effect transistors as amplifier elements whose first current connections are connected to a constant reference voltage. In addition, a method for mixing frequencies that uses this mixer stage is also disclosed.

Abstract: A mixer stage is provided that includes an oscillator, a first input, a second input, a first output, a second output, a set of four controllable amplifier elements, and a first current source. The mixer stage further includes at least one second current source in addition to the first current source, the first current source and the at least one second current source can each be switched on and off by an associated switching input that is connected to an associated oscillator output. Pairs of amplifier elements of the set of four together with at least one of the at least two current sources in its switched-on state form a differential amplifier for an input signal present at the first input and the second input. A method for mixing frequencies is also provided.