Abstract: An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.

Abstract: In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.