Abstract: An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.

Abstract: In the pointer circuit, only one static memory (1) is respectively individually allocated to each output ( . . . , A.sub.n-1, A.sub.n, A.sub.n+1, . . . ), of which each respectively has a pair of mutually complementary memory terminals (Q, Q). The two terminals are in two stored logical states ("1," "0") differing from one another. A memory terminal (Q) of each memory is connected with the output allocated to this memory. The memories are controlled by clock signals. This results in advantageous surface requirement and power loss low, as well as high speed.

Abstract: The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.

Abstract: A digital/analog converter has a neuron MOS transistor, a maintenance circuit which keeps the drain potential of the neuron MOS transistor constant, and a current source. A linear dynamic range in terms of large signal is possible, so that converters having a larger input word size than, for example, only two bits can be realized in a simple way with low dissipated power. Such converters are of significance particularly for ULSI circuits.

Abstract: A threshold logic circuit with a low space requirement includes a first and at least one second circuit portion, each of which has an evaluator circuit and at least two branches to be evaluated. A partial sum signal formed in the first circuit portion is jointly used for the at least one second circuit portion and is not formed separately in each case. The main advantage is a low chip area consumption.

Abstract: This invention relates to an electrically conductive shaped article made from thermoplastic materials which are reinforced with glass and steel fibers wherein said fibers are incorporated into the thermoplastic material by pultrusion. The amount of glass fibers incorporated into the thermoplastic material is such that the specific conductivity is at least 10% greater than in a shaped article in which the glass fibers are replaced by thermoplastic material. The shaped article can be used for shielding an article from electromagnetic radiation.

Abstract: A defined zero point voltage (V.sub.0), dependent on a settable zero point voltage target value (V.sub.0,soll), is enabled in amplifier stages (1 . . . k) with neuron MOS transistors (T10,1 . . . T10,k). This is generally required because, for example, due to a process-caused charging of the floating gates of the neuron MOS transistors, and due to a capacitively coupled-in voltage from the channel region, an undefined zero point displacement of the transmission characteristic curve results. The devices can be used together with the amplifier stages, e.g. in video and audio technology, in sensor technology, in analog computers, in fuzzy circuits and in neural networks.

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.

Abstract: A fine-grained polyether-ketone powder, having a particle size with a d.sub.50 value smaller than or equal to 40 .mu.m and a grain size distribution range smaller than or equal to 55 .mu.m, is obtained by cold-grinding of coarse-grained polyether-ketone in a fluid-bed opposed-jets mill, which is provided with a grinding chamber (2) subjected to gas jets, a grinding material-charging device, a screening device (5) for separating coarse material (11) and fine material (10), and a bottom (3) underneath the grinding chamber for added material to be ground and coarse material flowing back from the screening device, the material to be ground and the coarse material flowing back from the screening device being cooled by means of a cryogenic refrigerant.The powders obtained in this way are used for producing surface coatings or composites.

Abstract: Hot melt adhesive based on a polyarylene ether ketone of the formula--[--O--Ar(--L--Ar).sub.x --O--Ar--CO--(--Ar--M).sub.y --Ar--]--(I)for which the ether/ketone ratio is between 0.5 and 2 and the melt flowability MVI (400/10 min) is 2 to 250. These hot melt adhesives facilitate adhesive bonds, which are resistant to high temperatures, at composites composed of metallic, ceramic and/or polymer substrates which have very good shear strengths.

Abstract: Composites based on PEEKK and reinforcing fibers give moldings which have a high modulus of elasticity. The moldings have a higher rigidity and heat resistance in comparison with moldings produced from prior-art polyetherketones. The proportion of reinforcing fibers is 1 to 70% by weight. Composites of this type can be processed in standard injection molding machines.