Abstract: The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing bit information. According to the invention it is provided that the memory area (SB) can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area, and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed.

Abstract: The invention relates, inter alia, to a memory cell (10) comprising at least one binary memory area for storing bit information. According to the invention it is provided that the memory area (SB) can optionally store holes or electrons and allows a recombination of holes and electrons, the charge carrier type of the charge carriers stored in the memory area defines the bit information of the memory area, and a charge carrier injection device (PN) is present, by means of which optionally holes or electrons can be injected into the memory area (SB) and the bit information can thus be changed.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure.

Abstract: The invention relates, among other things, to a memory cell for storing at least one piece of bit data. Said memory cell comprises at least two electrical terminals and a semiconductor structure with a band curve (EL) that has at least one potential well. The charged state of the potential well with charge carries can be increased by applying a supply voltage (Us=Uspeis) to the two terminals, can be reduced by applying a discharge voltage (Us=Usperr), and can be maintained by applying a maintaining voltage (Us=Ubei), the respective charged state of the potential well defining the piece of bit data of the memory cell. According to the invention, the semiconductor structure has a space charge region (Wn) while the potential well is formed by a semiconductor heterostructure.