Abstract: The disclosure relates to a power converter package (100) for converting a first DC voltage and a second DC voltage into a common AC voltage. The power converter package comprises: a first power semiconductor (130) and a second power semiconductor (140); a first substrate (110); and a second substrate (120). The first substrate (110) comprises a first supply voltage area (113) being formed to supply the first DC voltage and a second supply voltage area (114) being formed to supply the second DC voltage. The first substrate (110) comprises a base metal area (115) being arranged on a first substrate lower main face (112). The base metal area (115) is configured to extract dissipated heat from the first power semiconductor (130) and the second power semiconductor (140). The second substrate (120) comprises an AC voltage output area (150) formed to provide the AC voltage.

Abstract: A hybrid bond sheet for bonding a first joining member to a second joining member, including: a core layer including: a core insulating layer formed between an upper main face and a lower main face of the core layer; and one or more metallic through-connections penetrating the core insulating layer from the upper main face to the lower main face. The hybrid bond sheet includes a first bonding layer with a first insulating bond layer and a first metal bond layer for bonding the first joining member. The hybrid bond sheet includes a second bonding layer with a second insulating bond layer and a second metal bond layer for bonding the second joining member. The one or more metallic through-connections and the first and second metal bond layers are configured to form an electrically and thermally conductive connection with the first joining member and the second joining member.

Abstract: A semiconductor power entity including a first laminate layer; a second laminate layer; an isolation layer arranged between the first laminate layer and the second laminate layer; a first metal layer arranged at a first laminate upper main face of the first laminate layer and a second metal layer arranged at a first laminate lower main face of the first laminate layer; a third metal layer arranged at a second laminate upper main face of the second laminate layer and a fourth metal layer arranged at a second laminate lower main face of the second laminate layer; and a connection metal layer embedded in the isolation layer between the first laminate layer and the second laminate layer, the connection metal layer forming an electrical connection with the second metal layer and the third metal layer.

Abstract: A hybrid bond sheet for mounting a semiconductor power module to a heat sink includes a thermally conductive core layer having an upper main face and a lower main face; a first bond layer formed at the upper main face of the core layer for bonding the hybrid bond sheet to a semiconductor power module; and a second bond layer formed at the lower main face of the core layer for bonding the hybrid bond sheet to a heat sink; where the core layer is subdivided into a plurality of core metal sections and core polymer sections which are formed side-by-side between the upper main face and the lower main face, the subdivided core metal sections being configured to enable a uniform heat transfer between the semiconductor power module and the heat sink and to reduce thermal stress at interfaces between the hybrid bond sheet and the heat sink.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and an array of contact elements electrically coupling the substrate to the semiconductor chip. The semiconductor device includes an underfill material between the substrate and the semiconductor chip and between the contact elements. A patterned structure is arranged on the substrate and extends from under the semiconductor chip through a keep-out zone around an edge of the semiconductor chip. The patterned structure provides a reservoir for the underfill material.

Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

Abstract: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.

Abstract: According to various examples, systems, methods, and devices for a light emitting device are described herein. As one example, a light emitting device includes a light emitting element and a capacitor. The capacitor is configured as a voltage buffer for the light emitting element and is further configured to dissipate heat from the light emitting element. According to another example, a carrier for a light emitting arrangement is described herein. According to this example, the carrier includes a capacitor configured to buffer a voltage of the light emitting arrangement. The carrier further includes a contacting structure configured for electrically contacting the light emitting arrangement and the capacitor. The capacitor and the contacting structure are arranged such that the capacitor is configured to dissipate heat from the light emitting arrangement.

Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Abstract: This invention relates to an apparatus, comprising: a plurality of plates in a stack defining at least one process layer and at least one heat exchange layer, each plate having a peripheral edge, the peripheral edge of each plate being welded to the peripheral edge of the next adjacent plate to provide a perimeter seal for the stack, the ratio of the average surface area of each of the adjacent plates to the average penetration of the weld between the adjacent plates being at least about 100 cm2/mm. The stack may be used as the core assembly for a microchannel processor. The microchannel processor may be used for conducting one or more unit operations, including chemical reactions such as SMR reactions.

Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

Abstract: A semiconductor device includes a substrate, a semiconductor chip, and an array of contact elements electrically coupling the substrate to the semiconductor chip. The semiconductor device includes an underfill material between the substrate and the semiconductor chip and between the contact elements. A patterned structure is arranged on the substrate and extends from under the semiconductor chip through a keep-out zone around an edge of the semiconductor chip. The patterned structure provides a reservoir for the underfill material.

Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

Abstract: According to various examples, systems, methods, and devices for a light emitting device are described herein. As one example, a light emitting device includes a light emitting element and a capacitor. The capacitor is configured as a voltage buffer for the light emitting element and is further configured to dissipate heat from the light emitting element. According to another example, a carrier for a light emitting arrangement is described herein. According to this example, the carrier includes a capacitor configured to buffer a voltage of the light emitting arrangement. The carrier further includes a contacting structure configured for electrically contacting the light emitting arrangement and the capacitor. The capacitor and the contacting structure are arranged such that the capacitor is configured to dissipate heat from the light emitting arrangement.

Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

Abstract: This invention relates to an apparatus, comprising: a plurality of plates in a stack defining at least one process layer and at least one heat exchange layer, each plate having a peripheral edge, the peripheral edge of each plate being welded to the peripheral edge of the next adjacent plate to provide a perimeter seal for the stack, the ratio of the average surface area of each of the adjacent plates to the average penetration of the weld between the adjacent plates being at least about 100 cm2/mm. The stack may be used as the core assembly for a microchannel processor. The microchannel processor may be used for conducting one or more unit operations, including chemical reactions such as SMR reactions.