Patents by Inventor Andreas Nowatzyk

Andreas Nowatzyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12147528
    Abstract: While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: November 19, 2024
    Assignee: VMware LLC
    Inventors: Irina Calciu, Andreas Nowatzyk, Pratap Subrahmanyam
  • Patent number: 12019554
    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 25, 2024
    Assignee: VMware LLC
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Patent number: 12008361
    Abstract: A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: June 11, 2024
    Assignee: VMware LLC
    Inventors: Irina Calciu, Andreas Nowatzyk, Pratap Subrahmanyam
  • Patent number: 11880309
    Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 23, 2024
    Assignee: VMware, Inc.
    Inventors: Nishchay Dua, Andreas Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Venkata Subhash Reddy Peddamallu, Adarsh Seethanadi Nayak
  • Patent number: 11782832
    Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: October 10, 2023
    Assignee: VMware, Inc.
    Inventors: Isam Wadih Akkawi, Andreas Nowatzyk, Pratap Subrahmanyam, Nishchay Dua, Adarsh Seethanadi Nayak, Venkata Subhash Reddy Peddamallu, Irina Calciu
  • Publication number: 20230205649
    Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
  • Patent number: 11620192
    Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 4, 2023
    Assignee: VMware, Inc.
    Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
  • Publication number: 20230069152
    Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: Isam Wadih AKKAWI, Andreas NOWATZYK, Pratap SUBRAHMANYAM, Nishchay DUA, Adarsh Seethanadi NAYAK, Venkata Subhash Reddy PEDDAMALLU, Irina CALCIU
  • Patent number: 11586545
    Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: February 21, 2023
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Publication number: 20230023256
    Abstract: A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.
    Type: Application
    Filed: September 28, 2021
    Publication date: January 26, 2023
    Inventors: Irina CALCIU, Andreas NOWATZYK, Pratap SUBRAHMANYAM
  • Publication number: 20230028825
    Abstract: A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.
    Type: Application
    Filed: November 19, 2021
    Publication date: January 26, 2023
    Inventors: Irina CALCIU, Andreas NOWATZYK, Pratap SUBRAHMANYAM
  • Publication number: 20230022096
    Abstract: While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Inventors: Irina CALCIU, Andreas NOWATZYK, Pratap SUBRAHMANYAM
  • Publication number: 20230004497
    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 5, 2023
    Inventors: Irina CALCIU, Andreas NOWATZYK, Isam Wadih AKKAWI, Venkata Subhash Reddy PEDDAMALLU, Pratap SUBRAHMANYAM
  • Publication number: 20230004496
    Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Inventors: Irina CALCIU, Andreas NOWATZYK, Isam Wadih AKKAWI, Venkata Subhash Reddy PEDDAMALLU, Pratap SUBRAHMANYAM
  • Patent number: 11544194
    Abstract: A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 3, 2023
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Pratap Subrahmanyam
  • Publication number: 20220414017
    Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: Nishchay DUA, Andreas NOWATZYK, Isam Wadih AKKAWI, Pratap SUBRAHMANYAM, Venkata Subhash Reddy PEDDAMALLU, Adarsh Seethanadi NAYAK
  • Patent number: 11442865
    Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: September 13, 2022
    Assignee: VMware, Inc.
    Inventors: Irina Calciu, Andreas Nowatzyk, Isam Wadih Akkawi, Venkata Subhash Reddy Peddamallu, Pratap Subrahmanyam
  • Publication number: 20220012139
    Abstract: Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a “remote memory” of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventors: Andreas Nowatzyk, Pratap Subrahmanyam, Isam Akkawi
  • Patent number: 10713978
    Abstract: A computing device includes memory configured for storing executable instructions, a processor configured for executing the instructions, a foldable display layer configured for displaying information in response to the execution of the instructions, and a bend limit layer coupled to the foldable display layer and arranged substantially parallel to a display surface of the foldable display layer. The bend limit layer is configured to increase its stiffness non-linearly when a radius of a bend of the bend limit layer is less than a threshold radius of curvature of the foldable display layer, the threshold radius of curvature being greater than 1 mm and less than 20 mm.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: July 14, 2020
    Assignee: GOOGLE LLC
    Inventors: William Riis Hamburgen, Yi Tao, Bruce Schena, James Cooper, John Stuart Fitch, Jeffrey Hayashida, Avi Hecht, Lawrence Lam, Andreas Nowatzyk, Jonathan Nivet, Kelvin Kwong, Kiarash Vakhshouri
  • Publication number: 20180348821
    Abstract: A computing device includes memory configured for storing executable instructions, a processor configured for executing the instructions, a foldable display layer configured for displaying information in response to the execution of the instructions, and a bend limit layer coupled to the foldable display layer and arranged substantially parallel to a display surface of the foldable display layer. The bend limit layer is configured to increase its stiffness non-linearly when a radius of a bend of the bend limit layer is less than a threshold radius of curvature of the foldable display layer, the threshold radius of curvature being greater than 1 mm and less than 20 mm.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 6, 2018
    Inventors: William Riis Hamburgen, Yi Tao, Bruce Schena, James Cooper, John Stuart Fitch, Jeffrey Hayashida, Avi Hecht, Lawrence Lam, Andreas Nowatzyk, Jonathan Nivet, Kelvin Kwong, Kiarash Vakhshouri