Abstract: A modular chiplet system enables numerous unique systems to be created from a small set of chiplets and a fabric device. The modular chiplet system includes an active semiconductor substrate with a built-in network-on-chip, chiplet interfaces for connecting to stacked chiplets, power delivery networks, clocking, system management, and general-purpose I/O. A set of mechanically and electrically interchangeable rotationally symmetrical chiplets can be connected to the active semiconductor interposer, at one site of an array of N×M sites. The rotational symmetry enables I/O chiplets to be placed at any side of the active semiconductor substrate. The modular chiplet system includes a shared memory architecture that allows the chiplets to communicate with each other using memory mapped addressing and read/write transactions that are routed by the network-on-chip. The network-on-chip also enables communication between resources on or accessible via the active semiconductor substrate.

Abstract: The present disclosure relates to a method for gathering and organizing media content in a social media is provided. The method initiates with providing a stream of postings of media content for a user account and receiving, from the user account, selection of media content provided within the stream. The selected media content is moved from the stream to a playlist interface. The selected media content is organized within the playlist interface into categories based on content type to generate a playlist for the user account. The organized playlist of the selected media content is provided for rendering at a display device that is used for accessing the user account.

Abstract: The present disclosure relates to a method for gathering and organizing media content in a social media is provided. The method initiates with providing a stream of postings of media content for a user account and receiving, from the user account, selection of media content provided within the stream. The selected media content is moved from the stream to a playlist interface. The selected media content is organized within the playlist interface into categories based on content type to generate a playlist for the user account. The organized playlist of the selected media content is provided for rendering at a display device that is used for accessing the user account.

Abstract: The present disclosure relates to a method for gathering and organizing media content in a social media is provided. The method initiates with providing a stream of postings of media content for a user account and receiving, from the user account, selection of media content provided within the stream. The selected media content is moved from the stream to a playlist interface. The selected media content is organized within the playlist interface into categories based on content type to generate a playlist for the user account. The organized playlist of the selected media content is provided for rendering at a display device that is used for accessing the user account.

Abstract: A mesh network has a plurality of nodes that can be arranged in a two or three dimensional arrangement. The address-based mesh routing scheme sends a full address and full data on every clock cycle. The system can include broadcasting to columns, rows, planes, or all system elements using a single data transaction. A selectable routing scheme can be random, fixed, or adaptive, depending on user configuration. A registered transaction-weight scheme is provided that can stall transactions in a mesh without having to resend data.

Abstract: A mesh network has a plurality of nodes that can be arranged in a two or three dimensional arrangement. The address-based mesh routing scheme sends a full address and full data on every clock cycle. The system can include broadcasting to columns, rows, planes, or all system elements using a single data transaction. A selectable routing scheme can be random, fixed, or adaptive, depending on user configuration. A registered transaction-weight scheme is provided that can stall transactions in a mesh without having to resend data.

Abstract: A DSP architecture achieves high code density and performance by using 16 bit encoding/decoding of three-register instructions and including orthogonal 64 register selection fields within a 32-bit instruction. A 64 entry register file allows high performance, while the 16-bit instruction size provides excellent code density in control type applications.

Abstract: A retention device stabilizes the logic output levels of a dynamic logic stage. The dynamic logic stage contains an inverter, which generates an inverted logic signal that is used as a feedback signal into the retention device. The retention device contains a switching element consisting of two active elements connected in series. The retention device has two inputs, a control input for receiving a delayed clock signal, and a feedback input for receiving the inverted logic signal generated by the inverter. The feedback and delayed clock signals switch the switching element between two retention states, where each retention state stabilizes a respective logic output level.