Abstract: Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).

Abstract: Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.

Abstract: Chip-support arrangement (23) with a chip support (23) for the manufacture of a chip casing, said chip support being provided on a support foil (20) with conducting paths (21) which are connected on the front side of the support foil facing a chip (39) to contact-surface metallizations (40) of the chip and which with their free ends form a connection-surface arrangement (42) distributed in planar manner for the purpose of connection to an electronic component or a substrate, whereby the conducting paths (21) are arranged on the reverse side of the support foil (20), recesses (28) in the support foil (20) are provided in the region of the contact-surface metallizations (40), the conducting paths for forming the connection-surface arrangement (42) are covered with a perforated mask (36) and the thickness (s) of the support foil is smaller than or substantially equal to the height (h) of the contact-surface metallizations (40) on the surface of the chip.