Patents by Inventor Andreas Riegler

Andreas Riegler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978693
    Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 7, 2024
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
  • Publication number: 20230261117
    Abstract: A trench junction field effect transistor (trench JFET) includes a mesa region confined by first and second trenches along a first lateral direction. The first and second trenches extend into a semiconductor body from a first surface of the semiconductor body. A mesa channel region of a first conductivity type is confined, along the first lateral direction, by first and second gate regions of a second conductivity type. A first pn junction is defined by the mesa channel region and the first gate region. A second pn junction is defined by the mesa channel region and the second gate region. The mesa channel region includes, along the first lateral direction, first, second and third mesa channel sub-regions having a same extent along the first lateral direction.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 17, 2023
    Inventors: Hans Weber, David Kammerlander, Andreas Riegler
  • Patent number: 11728790
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20230238294
    Abstract: A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 ?m.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 27, 2023
    Inventors: Christian Fachmann, Barbara Angela Glanzer, Andreas Riegler
  • Publication number: 20230238333
    Abstract: A semiconductor device includes a high-voltage semiconductor transistor chip having a front side and a backside. A low-voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. The semiconductor device further includes a dielectric inorganic substrate having a first side and a second side opposite the first side. A pattern of first metal structures runs through the dielectric inorganic substrate and is connected to the low-voltage load electrode. At least one second metal structure runs through the dielectric inorganic substrate and is connected to the control electrode. The front side of the semiconductor transistor chip is attached to the first side of the dielectric inorganic substrate. The dielectric inorganic substrate has a thickness measured between the first side and the second side of at least 50 ?m.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 27, 2023
    Inventors: Christian Fachmann, Barbara Angela Glanzer, Andreas Riegler
  • Publication number: 20230126534
    Abstract: A transistor device is disclosed.
    Type: Application
    Filed: January 19, 2021
    Publication date: April 27, 2023
    Inventors: Hans Weber, Björn Fischer, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20230075897
    Abstract: An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).
    Type: Application
    Filed: March 5, 2021
    Publication date: March 9, 2023
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Manfred Pippan, Andreas Riegler
  • Patent number: 11545561
    Abstract: A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Wolfgang Jantscher, Manfred Pippan, Maik Stegemann
  • Patent number: 11538008
    Abstract: A method to generate revenue from supplied content is provided. Content is provided to a consumer via a network by providing a content service that allows the consumer to select and retrieve content as a package together with a clearing of the selectable content to an operator used by the consumer to select and retrieve the content via the network. Any content selected by the consumer is supplied directly to the consumer via the operator. The operator is charged for the supplied content.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: December 27, 2022
    Assignee: Tahoe Research, Ltd.
    Inventors: Thomas Nemetz, Andreas Riegler, Andreas Spechtler
  • Patent number: 11527468
    Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andreas Riegler, Christian Fachmann, Matteo-Alessandro Kutschak, Carsten von Koblinski, Hans Weber
  • Publication number: 20220310838
    Abstract: A semiconductor device is proposed. An example of the semiconductor device includes a semiconductor body having a first main surface. A trench structure extends into the semiconductor body from the first main surface. The trench structure includes a trench electrode structure and a trench dielectric structure. The trench dielectric structure includes a gate dielectric in an upper part of the trench dielectric structure and a gap in a lower part of the trench dielectric structure. The semiconductor device further includes a body region adjoining the gate dielectric at a sidewall of the trench structure in the upper part of the trench dielectric structure. The gate dielectric extends deeper into the semiconductor body along the sidewall than the body region.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 29, 2022
    Inventors: Hans Weber, David Kammerlander, Andreas Riegler
  • Publication number: 20220231671
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11323099
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: May 3, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11289597
    Abstract: A transistor device is enclosed. The transistor device includes: a semiconductor body; a plurality of drift regions of a first doping type; a plurality of compensation regions of a second doping type adjoining the drift regions; and a plurality of transistor cells each including a body region adjoining a respective one of the plurality of drift regions, a source region adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The source regions of the plurality of transistor cells are connected to a source node, the body regions of the plurality of transistor cells are separated from the plurality of compensation regions in the semiconductor body, and the plurality of compensation regions are ohmically connected to the source node.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: March 29, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Björn Fischer, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20220077845
    Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.
    Type: Application
    Filed: March 5, 2021
    Publication date: March 10, 2022
    Inventors: Hans Weber, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Publication number: 20220037240
    Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Inventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
  • Publication number: 20220028699
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 27, 2022
    Inventors: Christian Fachmann, Barbara Angela Glanzer, Andreas Riegler
  • Publication number: 20210335696
    Abstract: A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: Andreas Riegler, Christian Fachmann
  • Publication number: 20210319419
    Abstract: A method to generate revenue from supplied content is provided. Content is provided to a consumer via a network by providing a content service that allows the consumer to select and retrieve content as a package together with a clearing of the selectable content to an operator used by the consumer to select and retrieve the content via the network. Any content selected by the consumer is supplied directly to the consumer via the operator. The operator is charged for the supplied content.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Thomas Nemetz, Andreas Riegler, Andreas Spechtler
  • Patent number: 11088275
    Abstract: A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler