Abstract: Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a first transistor, a second transistor, and a fuse with a first end and a second end. The second transistor is selectively operable to couple the first end of the fuse to a ground. The first bitline is coupled to the first transistor of each of the bitcells of one column. The second bitline is coupled to the second end of the fuse of each of the bitcells of the column. The first transistor of each of the bitcells of the column is selectively operable to couple the first end of the fuse to the first bitline.