Abstract: An oscillator circuit (300) comprising: a resonator (Q) connected between an input (IN)and an output (OUT); an inverter having first and second driver transistors (MP, MN) connected in series via an output-coupled node; first and second biasing transistors (MPD, MND) for biasing the driver transistors; and first and second limiting means between the gate electrodes of the driver transistors respectively and the output. The CMOS circuit allows regulation of the oscillation amplitude without need for well-controlled DC current sources to polarize correctly the driver transistors, and without need for a start-up circuit to ensure that both driver transistors remain in saturation when the circuit is powered on. A simple oscillator circuit (600) has an inverter whose input is capacitively coupled to the input (IN), first limiting means coupled between the inverter input and the output (OUT), and second limiting means coupled between the input (IN) and the output (OUT).

Abstract: An oscillator circuit (300) comprising: a resonator (Q) connected between an input (IN)and an output (OUT); an inverter having first and second driver transistors (MP, MN) connected in series via an output-coupled node; first and second biasing transistors (MPD, MND) for biasing the driver transistors; and first and second limiting means between the gate electrodes of the driver transistors respectively and the output. The CMOS circuit allows regulation of the oscillation amplitude without need for well-controlled DC current sources to polarize correctly the driver transistors, and without need for a start-up circuit to ensure that both driver transistors remain in saturation when the circuit is powered on. A simple oscillator circuit (600) has an inverter whose input is capacitively coupled to the input (IN), first limiting means coupled between the inverter input and the output (OUT), and second limiting means coupled between the input (IN) and the output (OUT).

Abstract: An oscillating circuit includes a low power inverting amplifier (10) having an input (208) and an output (209) and having a relatively high resistance d.c. biasing path (2) associated therewith. A relatively low resistance path (3) can be switched so as to couple the amplifier input (208) and output (209) together during a bias settling phase of the circuit. A detector (50) detects the voltage at either the amplifier input (208) or the output (209) and switches the relatively low resistance path (3) so that it does not couple the input (208) and output (209) together when the detected voltage reaches a level just before a required operating voltage level.

Abstract: A circuit including an operational amplifier (A) having an input stage comprising first and second transistors (10, 12) coupled in differential configuration and being powered by a first current source (20), the current source being powered by the output of the operational amplifier, wherein in order to ensure start up of the amplifier a second current source (34) is coupled to the differential pair of transistors, wherein a sensing means (40, 42) is provided responsive to the inputs of the operational amplifier and arranged to control energization of the second current source in order to switch off the second current source after switch on of the amplifier.

Abstract: A circuit for generating voltages having values proportional to the threshold voltages (V.sub.T) of n-channel transistors used in the circuit comprises a current mirror M.sub.2, M.sub.3 having a reference current input generated from a reference voltage of value 2V.sub.t by an n-channel transistor M.sub.1. The output reference voltage of value 2V.sub.T by an n-channel transistor M.sub.4 whose gate is coupled either to its drain, for output voltages greater than V.sub.T, or to the gate of transistor M.sub.1 for output voltages less then V.sub.T.

Abstract: A CMOS analog multiplying circuit comprising a first transistor (1) having its current electrodes coupled between a first reference voltage line and a first node and its gate electrode coupled to a first input node having, in use, an input voltage such that said first transistor operates in its triode region, a second transistor (2) having its current electrodes coupled between said first node and an output node, said output node being coupled to a second reference voltage line, and a comparator (3) for comparing a first voltage at said first node with a second voltage at a second input node and for controlling the gate electrode of said second transistor to keep said first and second voltages substantially equal, whereby the current through said second transistor is proportional to the product of the voltages at said first and second input nodes.

Abstract: A CMOS power-on detection circuit is described in which a rising supply potential is utilized to charge a capacitor and the voltage on the capacitor is coupled by one or more current mirrors to drive one of a pair of series connected complementary MOS transistors, a change in potential at a node between the transistors providing the power-on indication.

Abstract: A CMOS power on detection circuit is described which includes pairs of complementary MOS transistors being connected in series between two supply lines. Each pair of transistors includes a long and a short channel transistor. Biasing the transistors by the rising supply voltage and by the voltages on the nodes formed by the pairs respectively allows to reduce or to cut current consumption once the detection is performed.

Abstract: An electronic circuit for a high impedance probe for an instrument for measuring electrical voltages, comprising an input field effect transistor 15 connected in a source-follower configuration, a bipolar transistor 17 connected in an emitter-follower configuration and controlled by the transistor 15, a current source 18 serving as a load for the transistor 17, an amplifier 19 having a gain G which is slightly less than unity, the input of the amplifier being controlled by the transistor 15, and finally a resistor 20 which serves as a load for the transistor 15 and which connects the source of the transistor 15 to the output 8 of the amplifier 19, said output also serving as the output of the circuit, which is supplied by a voltage source applied between the current source 18 and the collector of the transistor 17. By virtue of the amplifier 19, the effective load resistance seen by the transistor 15 is R.sub.20 /(1-G), R.sub.20 being the value of the resistor 20.

Abstract: To regulate the threshold voltage of insulated-gate field-effect transistors (IGFETs) in an integrated circuit, such as that of an electronic wristwatch, capacitors and other IGFETs of the same conductivity type as those of the controlled circuit are incorporated in the substrate thereof to form a regulating transistor, a constant-current generator and one or more voltage multipliers. The current generator and the main electrodes (source and drain) of the regulating transistor, whose gate is tied to its source, are connected in series across a generator of reference voltage constituted by one or more such multipliers. One of the main electrodes of the regulating transistor is connected, directly or through a further voltage multiplier, to the reference terminal (O) of the controlled circuit while still another such multiplier may be inserted between the ouptut of the constant-current generator and the interconnected source and gate electrodes of the regulating transistor.

Abstract: A binary frequency divider stage comprises eleven insulated gate field effect transistors and a capacitor, all of which may be fabricated as an integrated circuit. The stage has an input, an output, two supply lines, and two clock lines for receiving two sets of out-of-phase clock pulses. Pulses are supplied to the input synchronously with one of the sets of clock pulses and the divider stage produces at its output pulses of half the frequency of the input pulses.

Abstract: An electronic circuit arrangement designed to store for an indefinite period a signal voltage of predetermined magnitude briefly applied thereto, comprises a main storage capacitor C.sub.s connected via a first semiconductor switch T.sub.1 across a supply of unipolar voltage and via a second semiconductor switch T.sub.2 across an ancillary storage capacitor C.sub.x, the latter lying in series with a binary capacitor C.sub.i between two conductors M, .PHI..sub.1 across which a clock pulse V.sub..PHI.1 is periodically generated. The semiconductor switches are field-effect transistors of the insulated-gate type (IGFETs), the gate of the first IGFET T.sub.1 being tied to the junction X between the ancillary storage capacitor C.sub.x and the gate of the binary capacitor C.sub.i ; this junction X communicates with the junction S between the two IGFETs and the main storage capacitor C.sub.s in the conductive state of the second IGFET T.sub.2 whose gate receives a series of unblocking pulses V.sub..PHI.

Abstract: A binary frequency-divider stage for an electronic wristwatch comprises a set of insulated-gate field-effect transistors (IGFETs) of one and the same conductivity type, one (T.sub.1) of these IGFETs and an associated series capacitor (C.sub.1) forming an amplifier located between one bus bar (M) of a d-c supply and a first one (11) of two a-c control leads carrying a pair of bipolar pulse trains (.PHI..sub.1, .PHI..sub.2) of opposite phase. An incoming pulse sequence (V.sub.E1), of a cadence to be halved, is in phase with the pulse train (.PHI..sub.2) on the other control lead (12) and may be derived directly therefrom (FIG. 5). The gate capacitance of the first IGFET (T.sub.1) can be charged in two steps by a first charging circuit including two IGFETs (T.sub.2, T.sub.3) which are alternately turned on by respective control pulses (.PHI..sub.1, .PHI..sub.2) applied to their gates. A normally blocked discharging circuit, including two other IGFETs (T.sub.4, T.sub.