Abstract: A chip device with a logic circuitry (105) protected by a randomized logic encryption based on a key (K) for preventing a designated usage of the logic circuitry (105) by an unauthorized user comprises: a physically unclonable function, PUF, (110), a storage (120), and a chip enabler (130) with one or more registers (132). The physically unclonable function, PUF, (110) is configured to generate a device-individual response (Re) based on a challenge (Ch). The storage (120) has stored the challenge (Ch) and a data element (C), the data element (C) being an encryption of the key (K) with the response (Re) of the PUF (110) as encryption key. The enabler (130) is configured to enable the logic circuitry (105) for the designated usage only, when the key (K) is transferred to the register(s) (132), the key (K) being a decryption of the data element (C) with the response (Re) as the encryption key.

Abstract: The invention relates to a 3D inkjet printing process for producing a component with a conductor body and an insulating body. The invention further relates to a component produced using the method. For reasons of simplicity, the application refers to the conductor body and the insulating body in the singular, which includes the plural.

Abstract: The 3D printing method disclosed here for the production of vascularized tissues and organs requires a droplet printer to produce photorealistic high-resolution prints and a device for applying non-directional or directional electromagnetic waves. The process uses a new type of capillary ink that crosslinks or undergoes a layer-forming reaction only in the edge area of the ink drops. Unbound capillary ink components are removed. The resulting cavities form a capillary network with diameters of up to approx. 10 ?m. Also disclosed is a novel printer table for supplying the printed tissue with medium during printing and a printer head supply unit for individually mixing the bio-inks from cell concentrate and various ink concentrates.

Abstract: A structure comprises: a plurality of substructures and a vernier-based position marker. The plurality of substructures include a first substructure, a second substructure, and at least one electronic component. The second substructure is at least partially additively manufactured on the first substructure. The vernier-based position marker is configured to indicate a relative offset between the first substructure and the second substructure.

Abstract: A chip device with a logic circuitry (105) protected by a randomized logic encryption based on a key (K) for preventing a designated usage of the logic circuitry (105) by an unauthorized user comprises: a physically unclonable function, PUF, (110), a storage (120), and a chip enabler (130) with one or more registers (132). The physically unclonable function, PUF, (110) is configured to generate a device-individual response (Re) based on a challenge (Ch). The storage (120) has stored the challenge (Ch) and a data element (C), the data element (C) being an encryption of the key (K) with the response (Re) of the PUF (110) as encryption key. The enabler (130) is configured to enable the logic circuitry (105) for the designated usage only, when the key (K) is transferred to the register(s) (132), the key (K) being a decryption of the data element (C) with the response (Re) as the encryption key.

Abstract: A circuit for broadband amplification is provided. The circuit includes an input HF_IN and an output HF_OUT, a first 90° hybrid coupler being connected to the input HF_IN of the circuit and a second 90° hybrid coupler being connected to the output HF_OUT of the circuit, and two amplifier stages being connected in parallel between the first and the second 90° hybrid coupler, the 90° hybrid couplers being hybrid couplers having an operating range of 1/n octaves between a lower frequency value and an upper frequency value, n?N\{0}, i.e., n is an element of the natural positive whole numbers in such a way that the upper frequency value is greater than the lower frequency range and simultaneously less than two times the value of the lower frequency range, and the amplifier stages being based on transistors having a III-nitride, or SiC, or diamond basis.

Abstract: The invention relates to a method and apparatus for shaping an input signal Son which is input to a multi-stage amplifier arrangement, to provide a definable output signal contour Soff. Individual amplifier stages are controlled by a control signal generated by a pulsed current source of a definable pulse length T. According to the invention, successive amplifier stages are each controlled (switched on) after a definable delay time ?ton 1, ?ton 2 following the preceding stage. Each amplifier stage has an assigned pulsed current source for generating the control signals of definable pulse length T. One such pulse generator respectively is assigned to each current source.

Abstract: In a method of generating a pulse-shaped transmitted output signal having a definable pulse shape in a multistage amplifier arrangement, the course of the “pulse top” (upper edge) of the transmitted signal is determined by control signals at the amplifier stages. The control signals of the amplifier stages are definable such that the control signal of an amplifier stage in each case comprises a number of pulse sections of a predefinable frame pulse. The tops of the pulse sections each having a predefinable constant gradient. A predistortion is introduced into the control signals in this manner, having a course which offsets distortion of the pulse top which results when no predistortion is used.

Abstract: A circuit for broadband amplification is provided. The circuit includes an input HF_IN and an output HF_OUT, a first 90° hybrid coupler being connected to the input HF_IN of the circuit and a second 90° hybrid coupler being connected to the output HF_OUT of the circuit, and two amplifier stages being connected in parallel between the first and the second 90° hybrid coupler, the 90° hybrid couplers being hybrid couplers having an operating range of 1/n octaves between a lower frequency value and an upper frequency value, n?N\{0}, i.e., n is an element of the natural positive whole numbers in such a way that the upper frequency value is greater than the lower frequency range and simultaneously less than two times the value of the lower frequency range, and the amplifier stages being based on transistors having a III-nitride, or SiC, or diamond basis.

Abstract: A procedure for operation of a high frequency amplifier having a power transistor—amplifier stage designed as a source or emitter circuit for amplifying a gate or base side high frequency signal supplied over an input interface network E which signal is amplified at the drain or collector side and output via an output interface network. A device for the measurement of the drain or collector current I_D is connected at the amplifier stage on the drain or collector side and a final control element is connected on the gate or base side. A pre-adjustable desired value W_SOLL and an actual value W_IST corresponding to the drain or collector current are input to the final control element, which adjusts the gate voltage or the base current so that the drain or collector current I_D is brought to the desired value W_SOLL. At a constant input power P_IN of the high frequency amplifier, the envelope curve of the output signal RF_OUT is modulated by the desired value W_SOLL.

Abstract: In a method and apparatus for of balancing the phases of a plurality of amplifier modules so as to maximize the combined power output of the amplifier modules an amplifier module is selected as a reference module with a fixed phase in a first step. In a second and subsequent steps, the phase of each of the other amplifier modules is each adjusted relative to the reference module, such that the combined power output from the respective individual amplifier module and the reference module is minimized. Finally, the phase of the reference module is rotated by 180°.

Abstract: A procedure for operation of a high frequency amplifier having a power transistor—amplifier stage designed as a source or emitter circuit for amplifying a gate or base side high frequency signal supplied over an input interface network E which signal is amplified at the drain or collector side and output via an output interface network. A device for the measurement of the drain or collector current I_D is connected at the amplifier stage on the drain or collector side and a final control element is connected on the gate or base side. A pre-adjustable desired value W_SOLL and an actual value W_IST corresponding to the drain or collector current are input to the final control element, which adjusts the gate voltage or the base current so that the drain or collector current I_D is brought to the desired value W_SOLL. At a constant input power P_IN of the high frequency amplifier, the envelope curve of the output signal RF_OUT is modulated by the desired value W_SOLL.

Abstract: The invention relates to a method and apparatus for shaping an input signal Son which is input to a multi-stage amplifier arrangement, to provide a definable output signal contour Soff. Individual amplifier stages are controlled by a control signal generated by a pulsed current source of a definable pulse length T. According to the invention, successive amplifier stages are each controlled (switched on) after a definable delay time ?ton 1, ?ton 2 following the preceding stage. Each amplifier stage has an assigned pulsed current source for generating the control signals of definable pulse length T. One such pulse generator respectively is assigned to each current source.

Abstract: In a method of generating a pulse-shaped transmitted output signal having a definable pulse shape in a multistage amplifier arrangement, the course of the “pulse top” (upper edge) of the transmitted signal is determined by control signals at the amplifier stages. The control signals of the amplifier stages are definable such that the control signal of an amplifier stage in each case comprises a number of pulse sections of a predefinable frame pulse. The tops of the pulse sections each having a predefinable constant gradient. A predistortion is introduced into the control signals in this manner, having a course which offsets distortion of the pulse top which results when no predistortion is used.

Abstract: In a method and apparatus for of balancing the phases of a plurality of amplifier modules so as to maximize the combined power output of the amplifier modules an amplifier module is selected as a reference module with a fixed phase in a first step. In a second and subsequent steps, the phase of each of the other amplifier modules is each adjusted relative to the reference module, such that the combined power output from the respective individual amplifier module and the reference module is minimized. Finally, the phase of the reference module is rotated by 180°.