Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Abstract: A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.

Abstract: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Abstract: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Abstract: A memory cell array includes reference cells each associated with a plurality of data cells of the array.

Abstract: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.

Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Abstract: A memory cell array includes reference cells each associated with a plurality of data cells of the array.

Abstract: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

Abstract: A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.

Abstract: A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Abstract: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.

Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract: A controlled CMOS substrate voltage generator generates a rectangular wave pulse which is supplied to the pumping circuit by a pumping capacitor and controlled decoupling members. At the same time the decoupling members are activated by a control circuit and are completely opened, so that the full pumping lift is completely utilized without reduction due to threshold voltages. In order to reduce the injection of charge carriers of nCMOS decoupling members, inversely activated pMOS decoupling members, which are strongly conducting at low substrate bias voltage near 0V, are connected in parallel to the latter. To increase performance, the circuit is designed as a circuit in phase opposition. Improved sensors are provided, which during the active phase maintain the shift of the substrate voltage produced upon wobble of the bit strings toward more negative values by alternation of the reference voltage of the sensor.