Abstract: For testing high-speed semiconductor memory devices (1) with a high data transfer rate, for instance DDR-DRAMs, controller modules (24) are provided in or as a constituent part of test receptacles (2) that are to be populated by a supply and handling system (3), said controller modules functionally essentially corresponding to customary graphic controllers. Components of the DRAMs (1) which determine the data transfer rate thereof are tested by means of the controller modules (24) at the supply and handling system (3), which is suitable for the high-volume throughout the DRAMs (1).

Abstract: For testing high-speed semiconductor memory devices with a high data transfer rate (such as DDR-DRAMs), in receiving units of supply and handling systems for tester apparatuses, selected graphic controllers are arranged on test assemblies, which are substantially structurally identical to graphics cards, and are connected via connecting lines to test receptacles for receiving the DRAMs. Components of the DRAMs that determine the data transfer rate thereof are tested by means of the graphic controllers at the supply and handling system.

Abstract: A method for calibrating a test apparatus for parallel testing of a number of semiconductor memories, to a time-critical parameter, in which the components are positioned in batches at predetermined test positions and the parameter is measured. The various test positions give different measurement results since they are not identical. These different measurement results are compensated for by the following steps: The invention provides for a position-specific mean value MPS to be formed from batch parameter measurements at each test position, for a position-independent mean value MPU to be formed for the batch parameter measurements at all the test positions, and for a corrected mean value to be obtained for each test position by adding a correction value &dgr;, which is determined from the difference between the position-specific mean value MPS and the position-independent mean value MPU, to the position-specific mean value MPS.

Abstract: A method for calibrating a test apparatus for parallel testing of a number of semiconductor memories, to a time-critical parameter, in which the components are positioned in batches at predetermined test positions and the parameter is measured. The various test positions give different measurement results since they are not identical. These different measurement results are compensated for by the following steps: The invention provides for a position-specific mean value MPS to be formed from batch parameter measurements at each test position, for a position-independent mean value MPU to be formed for the batch parameter measurements at all the test positions, and for a corrected mean value to be obtained for each test position by adding a correction value &dgr;, which is determined from the difference between the position-specific mean value MPS and the position-independent mean value MPU, to the position-specific mean value MPS.