Patents by Inventor Andreas Schlögl

Andreas Schlögl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200044064
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
  • Patent number: 10483383
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
  • Publication number: 20180269296
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 20, 2018
    Inventors: Joachim Weyers, Katarzyna Kowalik-Seidl, Andreas Schloegl, Enrique Vecino Vazquez
  • Patent number: 9748116
    Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Ulrich Froehler, Felix Grawert, Ernst Katzmaier, Uwe Kirchner, Rene Mente, Andreas Schloegl, Uwe Wahl
  • Publication number: 20170005025
    Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 5, 2017
    Inventors: Ralf OTREMBA, Ulrich FROEHLER, Felix GRAWERT, Ernst KATZMAIER, Uwe KIRCHNER, Rene MENTE, Andreas SCHLOEGL, Uwe WAHL
  • Publication number: 20160112041
    Abstract: A power transistor model is described which comprises a source drain path, a first current source and a voltage controlled second current source in the source drain path which model the static voltage-current-relationship of a modeled power transistor, wherein the voltage-controlled second current source models a nonlinear behavior of a drift zone of the power transistor.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Kevni Bueyuektas, Uwe Wahl, Andreas Schloegl, Gerhard Noebauer
  • Patent number: 9099454
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 4, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Publication number: 20150041967
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Patent number: 8680668
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8618644
    Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Veldvoss
  • Publication number: 20130069211
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Application
    Filed: February 28, 2012
    Publication date: March 21, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Publication number: 20120319109
    Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 20, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
  • Patent number: 8253225
    Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: August 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
  • Patent number: 8124449
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Patent number: 8097944
    Abstract: A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: January 17, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stefan Landau, Ralf Otremba, Uwe Kirchner, Andreas Schloegl, Christian Fachmann, Joachim Mahler
  • Publication number: 20100276797
    Abstract: A semiconductor device includes a substrate having a chip island, a chip attached to the chip island, and encapsulation material deposited on the chip and part of the chip island. The chip island includes a first main face to which the chip is attached opposite a second main face, with the second main face of the chip island defining at least one cavity.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Stefan Landau, Ralf Otremba, Uwe Kirchner, Andreas Schloegl, Christian Fachmann, Joachim Mahler
  • Publication number: 20100133666
    Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Georg Meyer-Berg, Andreas Schloegl
  • Publication number: 20090212284
    Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
  • Patent number: 6904128
    Abstract: A device (4) comprises a container (40) for a liquid coolant (41) that is disposed between the axis (1) and the surface (30) facing the axis to co-rotate with the surface. The device is further provided with an atomizer nozzle (42) of the container, facing the surface, from which the coolant is discharged during rotation of the container due to the centrifugal force (F) acting upon the coolant of the container in the form of an atomized jet (43) that strikes the surface. The device cools a surface of an electronic device (3) that runs hot, the electronic device supplying the X-ray source of a computer tomograph with power and rotating about the axis of the gantry (2) of the tomograph.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: June 7, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andreas Schlögl, Peter Tichy, Eckhard Wolfgang
  • Patent number: 6838729
    Abstract: The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an avalanche the voltage applied between two electrodes is 6 % or more above the static reverse voltage at the same temperature.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: January 4, 2005
    Assignee: Infineon Technologies AG
    Inventors: Andreas Schlögl, Markus Schmitt, Hans-Joachim Schulze, Markus Vossebürger, Armin Willmeroth