Patents by Inventor Andreas Schletz
Andreas Schletz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11749533Abstract: Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.Type: GrantFiled: April 19, 2021Date of Patent: September 5, 2023Assignee: Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V.Inventors: Steffen Ziesche, Christian Lenz, Uwe Waltrich, Christoph Bayer, Hoang Linh Bach, Andreas Schletz
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Publication number: 20230032223Abstract: This invention concerns a power module comprising a power device, a baseplate, circuit carrier, and a flat stacked aluminium electrolytic snubber capacitor comprising a layered structure of a cathode layer, a separator layer, comprising paper and an electrolyte and an anode layer, comprising an aluminium material with an aluminium oxide dielectric, wherein the circuit carrier are mounted on the baseplate, the power device and snubber capacitor are placed on the circuit carrier within the power module and electrically connected to the circuit carrier, the circuit carrier being configured for providing an electrical connection between the power device and the snubber capacitor.Type: ApplicationFiled: January 27, 2021Publication date: February 2, 2023Inventors: Thomas Ebel, Andreas Schletz
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Method for increasing the electrical functionality, and/or service life, of power electronic modules
Patent number: 11521899Abstract: In a method for increasing the electrical functionality, and/or service life, of power electronic modules, the power electronic circuit carrier, and/or the metallisation applied onto the power electronic circuit carrier, and/or a base plate connected, or to be connected, to a rear face of the power electronic circuit carrier, is finely structured by means of local material removal with at least one laser beam, so as to reduce thermomechanical stresses occurring during the production or operation of the module. In an alternative form of embodiment, the metallisation applied onto the front face of the power electronic circuit carrier is structured, or an already created structure is refined or supplemented, by means of local material removal with laser radiation, so as to achieve a prescribed electrical functionality of the metallisation.Type: GrantFiled: March 30, 2021Date of Patent: December 6, 2022Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Christoph Friedrich Bayer, Andreas Schletz -
Patent number: 11296054Abstract: A power semiconductor module, as well as a corresponding method of manufacture, are provided. The power semiconductor module has a plurality of power switches. A first subset of the power switches forms part of a first electrical current branch. A second subset of the power switches forms part of a second electrical current branch. Within the current branches, the associated power switches are arranged symmetrically with respect to the DC voltage contacts and are connected in such a way that a current density which is formed in the individual current paths which are respectively assigned to one of the power switches is at least substantially homogeneously distributed during the high frequency operation of the power semiconductor module and/or in the operation of the power switches with high voltage gradients.Type: GrantFiled: June 5, 2018Date of Patent: April 5, 2022Assignees: Fraunhofer-Gesellschaft, Bayerische Motoren Werke AktiengesellschaftInventors: Rene Richter, Thomas Schimanek, Maximillian Hofmann, Florian Hilpert, Andreas Schletz, Christoph Bayer, Uwe Waltrich
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Publication number: 20210327724Abstract: Disclosed is a method of manufacturing a power semiconductor component arrangement or a power semiconductor component housing. The method involves a sintering process in which the plurality of layer-shaped unsintered ceramic substrates are converted into a sintered ceramic single layer or multilayer substrate or into a sintered ceramic single layer or multilayer interconnect device. Also disclosed is a power semiconductor component arrangement or a power semiconductor component housing that can be manufactured using the above method. Further disclosed are the uses of the power semiconductor component arrangement or the power semiconductor component housing.Type: ApplicationFiled: April 19, 2021Publication date: October 21, 2021Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E. V.Inventors: Steffen ZIESCHE, Christian LENZ, Uwe WALTRICH, Christoph BAYER, Hoang Linh BACH, Andreas SCHLETZ
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METHOD FOR INCREASING THE ELECTRICAL FUNCTIONALITY, AND/OR SERVICE LIFE, OF POWER ELECTRONIC MODULES
Publication number: 20210327755Abstract: In a method for increasing the electrical functionality, and/or service life, of power electronic modules, the power electronic circuit carrier, and/or the metallisation applied onto the power electronic circuit carrier, and/or a base plate connected, or to be connected, to a rear face of the power electronic circuit carrier, is finely structured by means of local material removal with at least one laser beam, so as to reduce thermomechanical stresses occurring during the production or operation of the module. In an alternative form of embodiment, the metallisation applied onto the front face of the power electronic circuit carrier is structured, or an already created structure is refined or supplemented, by means of local material removal with laser radiation, so as to achieve a prescribed electrical functionality of the metallisation.Type: ApplicationFiled: March 30, 2021Publication date: October 21, 2021Inventors: Christoph Friedrich BAYER, Andreas SCHLETZ -
Publication number: 20210305197Abstract: In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.Type: ApplicationFiled: March 30, 2021Publication date: September 30, 2021Inventors: Yu ZECHUN, Christoph Friedrich BAYER, Andreas SCHLETZ
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Patent number: 10957684Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.Type: GrantFiled: November 19, 2019Date of Patent: March 23, 2021Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Tobias Erlbacher, Andreas Schletz, Gudrun Rattmann
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Publication number: 20200168597Abstract: In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.Type: ApplicationFiled: November 19, 2019Publication date: May 28, 2020Inventors: Tobias ERLBACHER, Andreas Schletz, Gudrun Rattmann
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Patent number: 10659035Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.Type: GrantFiled: October 1, 2019Date of Patent: May 19, 2020Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Tobias Erlbacher, Andreas Schletz
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Publication number: 20200152611Abstract: A power semiconductor module, as well as a corresponding method of manufacture, are provided. The power semiconductor module has a plurality of power switches. A first subset of the power switches forms part of a first electrical current branch. A second subset of the power switches forms part of a second electrical current branch. Within the current branches, the associated power switches are arranged symmetrically with respect to the DC voltage contacts and are connected in such a way that a current density which is formed in the individual current paths which are respectively assigned to one of the power switches is at least substantially homogeneously distributed during the high frequency operation of the power semiconductor module and/or in the operation of the power switches with high voltage gradients.Type: ApplicationFiled: June 5, 2018Publication date: May 14, 2020Inventors: Rene Richter, Thomas Schimanek, Maximillian Hofmann, Florian Hilpert, Andreas Schletz, Christoph Bayer, Uwe Waltrich
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Publication number: 20200112304Abstract: In a power module that has a carrier substrate with at least one unipolar semiconductor component as a power switch, the unipolar semiconductor component is configured such that a temperature rise of the semiconductor component, from a first temperature up to which the semiconductor component heats in operation at 50% full load, to a second temperature up to which the semiconductor component heats in operation at full load, is less than a temperature rise of the semiconductor component from an initial temperature at zero load to the first temperature. As a result of the reduced temperature rise between 50% and 100% full load the service life of the power module can be lengthened.Type: ApplicationFiled: October 1, 2019Publication date: April 9, 2020Inventors: TOBIAS ERLBACHER, ANDREAS SCHLETZ
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Publication number: 20180166413Abstract: The invention relates to the electrically conductive bond between at least two electrical components and/or devices at a carrier mounted with electronic and/or electrical devices, said bond being formed by a bond wire. The bond wire is bonded in a force fitting, shape matching manner and/or with material continuity to the electrical components and/or devices and is shaped in an arcuate manner between the electrical components and/or devices at a spacing from the surface of the carrier and from electronic and/or electrical devices arranged there. The respective bond wire is bent a multiple of times with changing directions between the electrical components and/or devices such that tips or regions of individual arcs are arranged at different spacings from the surface of the carrier.Type: ApplicationFiled: December 11, 2017Publication date: June 14, 2018Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Christoph Bayer, Uwe Waltrich, Andreas Schletz
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Patent number: 7800220Abstract: The invention concerns a power electronic arrangement comprising an insulating substrate, a cooling element arranged beneath the insulating substrate and one or more power electronic components disposed on a respective metallization surface of the insulating substrate. Disposed on the surface of the insulating substrate is a metal layer portion which projects beyond the insulating substrate at all sides. The region of the metal layer portion, that projects beyond the insulating substrate, forms a metal flange which borders the insulating substrate. The cooling element, on its side towards the insulating substrate, beneath the insulating substrate, has one or more recesses, whereby a cavity delimited by the insulating substrate and wall surfaces of the one or more recesses is formed beneath the insulating substrate for receiving a liquid cooling agent. The metal flange is further connected to the cooling element.Type: GrantFiled: February 9, 2007Date of Patent: September 21, 2010Assignee: ECPE Engineering Center for Power Electronics GmbHInventors: Martin Marz, Ernst Schimanek, Dieter Brunner, Andreas Schletz
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Publication number: 20090219694Abstract: The invention concerns a power electronic arrangement comprising an insulating substrate, a cooling element arranged beneath the insulating substrate and one or more power electronic components disposed on a respective metallization surface of the insulating substrate. Disposed on the surface of the insulating substrate is a metal layer portion which projects beyond the insulating substrate at all sides. The region of the metal layer portion, that projects beyond the insulating substrate, forms a metal flange which borders the insulating substrate. The cooling element, on its side towards the insulating substrate, beneath the insulating substrate, has one or more recesses, whereby a cavity delimited by the insulating substrate and wall surfaces of the one or more recesses is formed beneath the insulating substrate for receiving a liquid cooling agent. The metal flange is further connected to the cooling element.Type: ApplicationFiled: February 9, 2007Publication date: September 3, 2009Applicant: ECPE Engineering Center for Power Electronics GmbHInventors: Martin März, Ernst Schimanek, Dieter Brunner, Andreas Schletz