Patents by Inventor Andreas SEMBRANT
Andreas SEMBRANT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11615026Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: GrantFiled: January 31, 2022Date of Patent: March 28, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
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Patent number: 11354242Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: GrantFiled: May 29, 2020Date of Patent: June 7, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant
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Publication number: 20220156191Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
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Patent number: 11237969Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache locations buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: GrantFiled: August 3, 2020Date of Patent: February 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
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Publication number: 20200364144Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache locations buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
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Publication number: 20200293449Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Erik HAGERSTEN, Andreas SEMBRANT
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Patent number: 10754777Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at feast one processor (CPU), at least one cache private to the node and at least one cache location buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: GrantFiled: November 4, 2016Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
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Patent number: 10713166Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: GrantFiled: May 2, 2018Date of Patent: July 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant
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Patent number: 10671543Abstract: Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.Type: GrantFiled: November 20, 2014Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stefanos Kaxiras
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Patent number: 10409725Abstract: The execution or processing of an application can be adapted or modified based on a level of a cache in which a requested data block resides, by extracting level information from a cache hierarchy. When a request for a data block is made by a core to a cache memory system, the cache memory system extracts a level of a cache memory in which the data block resides from information stored in the cache memory system. The core is informed of the level of the cache memory in which the data block resides, and uses this information to adapt its processing of the application.Type: GrantFiled: May 1, 2015Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stafanos Kaxiras
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Patent number: 10402331Abstract: A computer processing system includes a plurality of nodes, each node having at least one processor core and at least one level of cache memory which is private to the node, a shared, last level cache (LLC) memory device and a shared, last level cache location buffer containing cache location entries, each cache location entry storing an address tag and a plurality of location information. The location information stored in a cache location entry points to an identified cacheline location within the LLC that stores a cacheline associated with the location information. The cacheline stored in the LLC has associated information identifying the cache location entry.Type: GrantFiled: May 1, 2015Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stefanos Kaxiras
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Patent number: 10402344Abstract: Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.Type: GrantFiled: November 20, 2014Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer, Stefanos Kaxiras
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Publication number: 20180329819Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at feast one processor (CPU), at least one cache private to the node and at least one cache location buffer {CLB} private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: ApplicationFiled: November 4, 2016Publication date: November 15, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
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Publication number: 20180322053Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.Type: ApplicationFiled: May 2, 2018Publication date: November 8, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Erik HAGERSTEN, Andreas Sembrant
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Patent number: 10031849Abstract: Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline.Type: GrantFiled: May 1, 2015Date of Patent: July 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
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Patent number: 10019368Abstract: A placement policy enables the selective storage of cachelines in a multi-level cache hierarchy: Reuse behavior of a cacheline is tracked during execution of an application in both a first level cache memory and a second level cache memory. A cache placement policy for the cacheline is determined based on the tracked reuse behavior.Type: GrantFiled: May 1, 2015Date of Patent: July 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Erik Hagersten, Andreas Sembrant, David Black-Schaffer
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Publication number: 20150347297Abstract: A computer processing system includes a plurality of nodes, each node having at least one processor core and at least one level of cache memory which is private to the node, a shared, last level cache (LLC) memory device and a shared, last level cache location buffer containing cache location entries, each cache location entry storing an address tag and a plurality of location information. The location information stored in a cache location entry points to an identified cacheline location within the LLC that stores a cacheline associated with the location information. The cacheline stored in the LLC has associated information identifying the cache location entry.Type: ApplicationFiled: May 1, 2015Publication date: December 3, 2015Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER, Stefanos KAXIRAS
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Publication number: 20150347299Abstract: A placement policy enables the selective storage of cachelines in a multi-level cache hierarchy: Reuse behavior of a cacheline is tracked during execution of an application in both a first level cache memory and a second level cache memory. A cache placement policy for the cacheline is determined based on the tracked reuse behavior.Type: ApplicationFiled: May 1, 2015Publication date: December 3, 2015Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER
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Publication number: 20150347302Abstract: The execution or processing of an application can be adapted or modified based on a level of a cache in which a requested data block resides, by extracting level information from a cache hierarchy. When a request for a data block is made by a core to a cache memory system, the cache memory system extracts a level of a cache memory in which the data block resides from information stored in the cache memory system. The core is informed of the level of the cache memory in which the data block resides, and uses this information to adapt its processing of the application.Type: ApplicationFiled: May 1, 2015Publication date: December 3, 2015Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER, Stefanos KAXIRAS
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Publication number: 20150347298Abstract: Data can be stored in a multi-level cache hierarchy memory system by, for example, storing valid data associated with a cacheline in a primary location in a first cache memory location. The first cache memory also stores location information about an alternative location in a second cache memory associated with the cacheline. Space is allocated in the alternative location of the second cache memory to store data associated with the cacheline.Type: ApplicationFiled: May 1, 2015Publication date: December 3, 2015Inventors: Erik HAGERSTEN, Andreas SEMBRANT, David BLACK-SCHAFFER