Patents by Inventor Andreas Sibrai
Andreas Sibrai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230376770Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.Type: ApplicationFiled: February 8, 2023Publication date: November 23, 2023Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI
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Patent number: 11755850Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.Type: GrantFiled: June 29, 2021Date of Patent: September 12, 2023Inventors: David Schie, Sergey Gaitukevich, Peter Drabos, Andreas Sibrai, Erik Sibrai
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Publication number: 20230206077Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.Type: ApplicationFiled: February 8, 2023Publication date: June 29, 2023Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI
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Publication number: 20230186089Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.Type: ApplicationFiled: February 7, 2023Publication date: June 15, 2023Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI
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Patent number: 11604996Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.Type: GrantFiled: April 26, 2019Date of Patent: March 14, 2023Assignee: AIStorm, Inc.Inventors: David Schie, Sergey Gaitukevich, Peter Drabos, Andreas Sibrai
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Patent number: 11494628Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.Type: GrantFiled: March 4, 2019Date of Patent: November 8, 2022Assignee: AISTORM, INC.Inventors: David Schie, Sergey Gaitukevich, Peter Drabos, Andreas Sibrai, Erik Sibrai
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Publication number: 20210326539Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET, An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.Type: ApplicationFiled: June 29, 2021Publication date: October 21, 2021Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI, ERIK SIBRAI
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Patent number: 11087099Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.Type: GrantFiled: March 4, 2019Date of Patent: August 10, 2021Assignee: AISTORM, INC.Inventors: David Schie, Sergey Gaitukevich, Peter Drabos, Andreas Sibrai, Erik Sibrai
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Publication number: 20200110987Abstract: A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.Type: ApplicationFiled: October 9, 2019Publication date: April 9, 2020Applicant: AISTORM INC.Inventors: David SCHIE, Peter DRABOS, Andreas SIBRAI, Erik SIBRAI
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Publication number: 20190332929Abstract: An event driven device has a network collecting data. A device is coupled to the network for determining changes in the data collected, wherein the device signals the network to process the data collected when the device determines desired changes in the data collected. In a second embodiment a level shift adjusts the band diagram of a spill and fill circuit to allow processing only if a change in input value occurs. This is extended to teach a means by which the subset of an image or incoming audio data might be used to trigger an event. It could also be used for always on operation at lower power than alternative solutions.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI
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Publication number: 20190332459Abstract: A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.Type: ApplicationFiled: April 26, 2019Publication date: October 31, 2019Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI
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Publication number: 20190286977Abstract: A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.Type: ApplicationFiled: March 4, 2019Publication date: September 19, 2019Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI, ERIK SIBRAI
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Publication number: 20190272395Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.Type: ApplicationFiled: March 4, 2019Publication date: September 5, 2019Inventors: DAVID SCHIE, SERGEY GAITUKEVICH, PETER DRABOS, ANDREAS SIBRAI, ERIK SIBRAI
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Patent number: 7583127Abstract: A voltage controlled variable capacitor, formed of a larger number of fixed capacitor segments and a corresponding number of switching elements, uses translinear amplifiers to control each switching element. Each translinear amplifier linearly switches from the fully off to the fully on state; a minimum number of switching stages (ideally only one) is in the mode-of-change at any one time with a minimum overlap. The arrangement achieves a nearly linear change of capacitance at linear tuning voltage change, while resulting in high Q-factor due to the low RDSon and high RDSoff of the fully switched stages. The invention eliminates temperature and voltage dependencies of other solutions like varactor diodes.Type: GrantFiled: January 26, 2004Date of Patent: September 1, 2009Assignee: Dialog Semiconductor GmbHInventors: Andreas Sibrai, Josef Niederl
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Patent number: 7265459Abstract: A voltage controlled variable capacitor, formed of a larger number of fixed capacitor segments and a corresponding number of switching elements, linearly switches on each switching element, one after the other. Several techniques are disclosed to have only a minimum number of switching stages being in the active mode-of-change at any one time with a minimum overlap. The arrangement achieves a nearly linear change of capacitance versus tuning voltage change, while resulting in high Q-factor due to the low RDSon and high RDSoff of the fully switched stages.Type: GrantFiled: January 26, 2004Date of Patent: September 4, 2007Assignee: Dialog Semiconductor GmbHInventors: Andreas Sibrai, Josef Niederl
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Patent number: 7154733Abstract: A circuit and a method are given, to realize a very efficient driver device for igniters or squibs as used e.g. in airbag applications. Special attention has been turned to include secure and always reliable operating features into the device and at the same time to reach for a low-cost implementation with modern integrated circuit technologies. Controlled firing operation and sophisticated diagnostic mechanisms are realized. These design features have been acquired by use of current mirror circuit principles for the switching devices where appropriate and with special regard to production cost. Current trimming and limitation to secure values are part of the solution.Type: GrantFiled: April 22, 2004Date of Patent: December 26, 2006Assignee: Dialog Semiconductor GmbHInventor: Andreas Sibrai
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Patent number: 7142407Abstract: A circuit and a method are given, to realize a very efficient driver device for igniters or squibs as used e.g. in airbag applications. Special attention has been turned to include secure and always reliable operating features into the device and at the same time to reach for a low-cost implementation with modern integrated circuit technologies. Controlled firing operation and sophisticated diagnostic mechanisms are realized. These design features have to a great extent been acquired by consequently using current mirror circuit principles. Current trimming and limitation to secure values are part of the solution.Type: GrantFiled: April 21, 2004Date of Patent: November 28, 2006Assignee: Dialog Semiconductor GmbHInventor: Andreas Sibrai
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Patent number: 7061339Abstract: Methods to achieve low power consumption, high output amplitude and an improved high frequency stability, and high speed for voltage-controlled oscillators are disclosed These methods includes to provide a current mirror, a power supply voltage Vdd, two single-ended outputs, a lower layer of gain providing structure comprising cross-coupled transistors, an upper layer of gain providing structure, a control voltage, a pair of capacitors to block a DC-connection to the gates of said cross-coupled transistors, a pair of resistors, and an LC-tank. Important steps of these methods include to set the time instances when said transistors of lower layer of gain providing structure open and close, to shut-down the transistors of lower layer of gain providing structure as soon as the energy required to keep the oscillations in said LC-tank is secured, to add additional gain in the amplification loop; and to pump-out charges of the channels of said transistors of said lower layer gain providing structure.Type: GrantFiled: December 8, 2004Date of Patent: June 13, 2006Assignee: Dialog Semiconductor GmbHInventors: Andreas Sibrai, Nikolay Tchamov
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Patent number: 6982601Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.Type: GrantFiled: October 20, 2004Date of Patent: January 3, 2006Assignee: Dialog Semiconductor GmbHInventor: Andreas Sibrai
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Publication number: 20050225925Abstract: A circuit and a method are given, to realize a very efficient driver device for igniters or squibs as used e.g. in airbag applications. Special attention has been turned to include secure and always reliable operating features into the device and at the same time to reach for a low-cost implementation with modern integrated circuit technologies. Controlled firing operation and sophisticated diagnostic mechanisms are realized. These design features have been acquired by use of current mirror circuit principles for the switching devices where appropriate and with special regard to production cost. Current trimming and limitation to secure values are part of the solution.Type: ApplicationFiled: April 22, 2004Publication date: October 13, 2005Inventor: Andreas Sibrai