Abstract: The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

Abstract: The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

Abstract: A method for error registration and a register which is assigned to a dual-computer system, information in the form of bits being stored in the register, the dual-computer system including an error-detection mechanism, and the bits in the register as error bits representing at least one error signal of the error-detection mechanism.

Abstract: A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a first operating mode and a second operating mode. In the first operating mode, both execution units are supplied with the same operands, and in the second operating mode different operands are supplied to both execution units, and both execution units are controlled by the same control signals for the processing of the operands in the first operating mode, and both execution units are controlled by different control signals for the processing of the operands in the second operating mode.

Abstract: A delay unit and a method for delaying accesses to data and/or instructions of a two-computer system having a first and a second computer, the first and the second computer operating with a time offset, and the delay unit being embodied in such a way that that time offset is compensated for in the two-computer system in the context of the accesses to data and/or instructions in at least one of the two computers, as well as a method and delay unit for delaying accesses to data and/or instructions of a computer system having error discovery mechanisms for error detection, wherein the time span between undelayed access to data and/or instructions and error detection is compensated for.

Abstract: A method and a device are described for switching between at least two operating modes of a processor unit including at least two execution units for running programs, at least one identifier being assigned to at least the programs which differentiates between the at least two operating modes, and switching between the operating modes is performed as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.

Abstract: A method and a device for correcting errors in a processor having two execution units as well as a corresponding processor, in which registers are provided in which instructions and/or associated information can be stored, the instructions being processed redundantly in both execution units and comparison means being included, and being such that by comparing the instructions and/or the associated information a deviation and thus an error is detected, a division of the registers of the processor into first registers and second registers being provided, the first registers being such that a specifiable state of the processor and contents of the second registers are derivable from them, means for a rollback being included, which are such that at least one instruction and/or the information in the first registers are rolled back and are executed anew and/or restored.