Abstract: A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Abstract: An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.

Abstract: In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

Abstract: A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.

Abstract: An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.

Abstract: Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier.

Abstract: The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.

Abstract: A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.

Abstract: In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

Abstract: A memory system includes a plurality of resistive memory cell fields including at least a first resistive memory cell field and a second resistive memory cell field, the first resistive memory cell field formed with a plurality of resistive memory cells storing data at a first data storage speed, the second resistive memory cell field formed with a plurality of resistive memory cells storing data at a second data storage speed lower than the first data storage speed, and a controller controlling data transfer between the plurality of resistive memory cell fields.

Abstract: The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL Circuit comprises a plurality of delay elements all having the same delay time and being connected in series to form a delay chain, wherein the periodic input signal is applied to the first delay element of the delay chain. The DLL circuit further comprises a detection unit which is connected to the outputs of at least a portion of the delay elements and which is provided to determine which delay element a particular edge of the periodic signal has reached after a predetermined phase progress of the periodic signal, and to generate a corresponding control information which indicates at which delay element the particular edge of the periodic signal has last been determined.

Abstract: A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.

Abstract: A device for generating memory-internal command signals from a memory operation command is provided comprising a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal and an output for applying the memory-internal command signal to a command signal line of the memory system. The device further includes a command signal generating means which is implemented in order to generate the memory-internal command signal using the memory operation command at a time which depends on the memory-internal command signal and which is selectively settable synchronous with a rising or synchronous with a falling edge of the external clock signal.