Abstract: An integrated circuit for receiving data includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths being connected in parallel. The first signal path includes a first comparator circuit that is connected, via a delay circuit and an amplifier circuit, to an output connection of the integrated circuit. The second signal path includes a second comparator circuit that is likewise connected, via a first inverter circuit and a second inverter circuit, to the output connection of the integrated circuit. The two amplifier circuits act as edge discriminators that drive each other and make it possible to generate, at the output connection, an output signal with the same duty cycle as the data signal without distortion.

Abstract: A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises a first amplifier stage and a second amplifier stage connected downstream of the first amplifier stage, and a device for actively setting a first operating point of the multistage input amplifier circuit. The multistage input circuit provides the external digital data signal in amplified form at an output and the device generates a bias potential for driving the input multistage amplifier circuit on the basis of the circuit topography of the multistage input amplifier circuit. The bias potential is used to set a second operating point of the first amplifier stage in such a manner that its output signal is within a prescribed third operating point of the second amplifier stage.

Abstract: An integrated circuit for receiving data includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths being connected in parallel. The first signal path includes a first comparator circuit that is connected, via a delay circuit and an amplifier circuit, to an output connection of the integrated circuit. The second signal path includes a second comparator circuit that is likewise connected, via a first inverter circuit and a second inverter circuit, to the output connection of the integrated circuit. The two amplifier circuits act as edge discriminators that drive each other and make it possible to generate, at the output connection, an output signal with the same duty cycle as the data signal without distortion.

Abstract: A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.

Abstract: A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises a first amplifier stage and a second amplifier stage connected downstream of the first amplifier stage, and a device for actively setting a first operating point of the multistage input amplifier circuit. The multistage input circuit provides the external digital data signal in amplified form at an output and the device generates a bias potential for driving the input multistage amplifier circuit on the basis of the circuit topography of the multistage input amplifier circuit. The bias potential is used to set a second operating point of the first amplifier stage in such a manner that its output signal is within a prescribed third operating point of the second amplifier stage.

Abstract: The invention relates to a semiconductor memory apparatus in which the connections of the connecting contacts can be varied. The invention also relates to a semiconductor apparatus which comprises at least two semiconductor memory apparatuses according to the invention.

Abstract: A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.

Abstract: The invention relates to a method for reading data with a data burst length (BL) greater than two from a semiconductor memory apparatus, comprising the following steps:

Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

Abstract: The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested independently of the other circuit components. The circuit component which is to be tested and the method for testing the circuit component are distinguished in that steps are taken to ensure that, during testing, the circuit component which is tested, outputs no data to the bus, and/or instead of the data which would need to be output to the bus during normal operation, outputs other data to the bus.

Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups being provided which each have transistor pairs having the same transistor line width. If there are m different driver transistor groups present, 2(n−1) different gradations result, thereby achieving good scalability. Furthermore, a transistor line width that is simple to design is provided for all transistors of all driver transistor groups, thereby providing identical electrical properties with respect to an output terminal unit.

Abstract: A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

Abstract: A test configuration for a parallel functional testing of semiconductor memory modules includes a test unit which provides a test sequence, feeds it to a module to be tested, and receives response signals generated by the module to be tested after the test sequence has been run through. A test logic circuit, which is connected to the test unit, receives the test sequence and is disposed on the module to be tested. The test unit is connected to the test logic circuit via a narrow interface for a bidirectional communication. For this purpose, the module to be tested has ports for connecting the interface. Only one of the ports serves for outputting of data to be read out from the module. This allows testing a large number of memory modules in parallel.

Abstract: The invention provides a circuit arrangement for scalable output drivers, symmetrically arranged driver transistor groups (504) being provided which each have transistor pairs (104, 105) having the same transistor line width (201). If there are m different driver transistor groups (504) present, 2(n-1) different gradations result, thereby achieving good scalability. Furthermore, a transistor line width (201, B) that is simple to design is provided for all transistors (104, 105) of all driver transistor groups (504), thereby providing identical electrical properties with respect to an output terminal unit (101).

Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Abstract: The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.