Abstract: A network device is provided. The device includes a housing and a switch card, mounted within the housing and having one or more connectors. A plurality of line cards are oriented parallel to each other and orthogonal to the switch card and assembled to the one or more connectors of the switch card. The switch card has a chip, with a plurality of switches or routing paths, and the switch card and the chip couple to the plurality of line cards through the one or more connectors.

Abstract: A network device is provided. The device includes a housing and a switch card, mounted within the housing and having one or more connectors. A plurality of line cards are oriented parallel to each other and orthogonal to the switch card and assembled to the one or more connectors of the switch card. The switch card has a chip, with a plurality of switches or routing paths, and the switch card and the chip couple to the plurality of line cards through the one or more connectors.

Abstract: A method for cooling electronic equipment. The method including propagating air through a first electronic component of the electronic equipment into a first enclosed area, where propagating the air through the first electronic component cools the first electronic component, circulating a refrigerant in a cooling loop, where the cooling loop comprises a heat exchanger, and propagating the air out of the first enclosed area by passing through the heat exchanger into a second enclosed area, where the air is cooled by passing through the heat exchanger.

Abstract: The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied—based on actual network traffic loading and congestion encountered.

Abstract: A rackmount storage server has a printed circuit board (PCB) having connectors for connecting with a plurality of top-loading storage devices. A controller assembly having a PCI expansion slot, is arranged to operatively connect to the passive backplane from a rear side of the PCB. Further, the rackmount storage server has redundant cooling unit for facilitating air flow in an interior region of the rackmount storage server. Further, the rackmount storage server may have an integrated battery for saving power for use in case of, for example, a power failure.

Abstract: A high speed communications interface divides data into a plurality of lanes, each lane encoded with clocking information, serialized, and sent to an interface. During cycles when there is no available data to send, IDLE_EVEN and IDLE_ODD cells are sent on alternating cycles. Data is transmitted by sending a header which spans all lanes and includes a START symbol. The final data transaction includes a Frame Check Sequence (FCS) which operates over the entire header and data. The packet is terminated by an END symbol, which is sent after the final data, and the remainder of the lanes are padded with IDLE_EVEN, IDLE_ODD, IDLE_EVEN_BUSY, or IDLE_ODD_BUSY cycles. The interface has a variable clock rate.

Abstract: The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied—based on actual network traffic loading and congestion encountered.

Abstract: A method for cooling electronic equipment. The method including propagating air through a first electronic component of the electronic equipment into a first enclosed area, where propagating the air through the first electronic component cools the first electronic component, circulating a refrigerant in a cooling loop, where the cooling loop comprises a heat exchanger, and propagating the air out of the first enclosed area by passing through the heat exchanger into a second enclosed area, where the air is cooled by passing through the heat exchanger.

Abstract: The invention provides an enhanced datagram packet switched computer network. The invention processes network datagram packets in network devices as separate flows, based on the source-destination address pair in the datagram packet. As a result, the network can control and manage each flow of datagrams in a segregated fashion. The processing steps that can be specified for each flow include traffic management, flow control, packet forwarding, access control, and other network management functions. The ability to control network traffic on a per flow basis allows for the efficient handling of a wide range and a large variety of network traffic, as is typical in large-scale computer networks, including video and multimedia traffic. The amount of buffer resources and bandwidth resources assigned to each flow can be individually controlled by network management. In the dynamic operation of the network, these resources can be varied—based on actual network traffic loading and congestion encountered.

Abstract: A blade server includes a chassis; a first plurality of bays in the chassis, wherein the first plurality of bays is adapted to receive and at least partially house a plurality of CPU modules, and wherein the first plurality of bays is accessible through a first side of the chassis; a second plurality of bays in the chassis, wherein the second plurality of bays is adapted to receive and at least partially house a plurality of PCI-Express modules, and wherein the second plurality of bays is accessible through a second side of the chassis; and a midplane board arranged to pass a PCI-Express signal between at least one of the plurality of CPU modules and at least one of the plurality of PCI-Express modules.

Abstract: A rackmount storage server has a printed circuit board (PCB) having connectors for connecting with a plurality of top-loading storage devices. A controller assembly having a PCI expansion slot, is arranged to operatively connect to the passive backplane from a rear side of the PCB. Further, the rackmount storage server has redundant cooling unit for facilitating air flow in an interior region of the rackmount storage server. Further, the rackmount storage server may have an integrated battery for saving power for use in case of, for example, a power failure.

Abstract: A rackmount server has dual-redundant hot-swappable fans for uniformly providing air flow to a plurality of CPU modules housed in the rackmount server. Air flow generated by the fans may also be provided to I/O circuitry disposed in the rackmount server. An airflow zone in which air flow is provided by the fans is separate, however, from an airflow zone in which air flow is provided to at least one power supply and/or disk drive housed in the rackmount server.

Abstract: Provided is a 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.

Abstract: The invention provides a method and system for packet processing, in which a router (or switch) is capable of quickly processing incoming packets, thus performing level 2, 3, and 4 routing and additional services, in real time. A system includes a packet processing engine (PPE), having elements for receiving packets, distinguishing header and payload information for those packets, outsourcing router decision-making to additional hardware resources such as a fast forwarding engine (FFE), and forwarding those packets. The PPE is synchronized to the FFE, so that the PPE can send and the FFE can receive packets at each one of a sequence of constant-duration time quanta. Similarly, the PPE can receive and the FFE can send packet routing information at each one of a sequence of similar time quanta. The PPE and the FFE have separate hardware so that their functions can be performed in parallel without contention for operating resources.

Abstract: The present invention provides a per-flow dynamic buffer management scheme for a data communications device. With per-flow dynamic buffer limiting, the header information for each packet is mapped into an entry in a flow table, with a separate flow table provided for each output queue. Each flow table entry maintains a buffer count for the packets currently in the queue for each flow. On each packet enqueuing action, a dynamic buffer limit is computed for the flow and compared against the buffer count already used by the flow to make a mark, drop, or enqueue decision. A packet in a flow is dropped or marked if the buffer count is above the limit. Otherwise, the packet is enqueued and the buffer count incremented by the amount used by the newly-enqueued packet. The scheme operates independently of packet data rate and flow behavior, providing means for rapidly discriminating well-behaved flows from non-well-behaved flows in order to manage buffer allocation accordingly.

Abstract: The invention provides for hardware processing of ACLs and thus hardware enforcement of access control. A sequence of access control specifiers from an ACL are recorded in a CAM, and information from the packet header is used to attempt to match selected source and destination IP addresses or subnets, ports, and protocols, against all the ACL specifiers at once. Successful matches are input to a priority selector, which selects the match with the highest priority (that is, the match that is first in the sequence of access control specifiers). The specified result of the selected match is used to permit or deny access for the packet without need for software processing, preferably at a rate comparable to wirespeed. The CAM includes an ordered sequence of entries, each of which has an array of ternary-elements for matching “0”, “1”, or any value, and each of which generates a match signal.

Abstract: A high speed communications interface divides data into a plurality of lanes, each lane encoded with clocking information, serialized, and sent to an interface. During cycles when there is no available data to send, IDLE_EVEN and IDLE_ODD cells are sent on alternating cycles. Data is transmitted by sending a header which spans all lanes and includes a START symbol. The final data transaction includes a Frame Check Sequence (FCS) which operates over the entire header and data. The packet is terminated by an END symbol, which is sent after the final data, and the remainder of the lanes are padded with IDLE_EVEN, IDLE_ODD, IDLE_EVEN_BUSY, or IDLE_ODD_BUSY cycles. The interface has a variable clock rate.

Abstract: The present invention provides a per-flow dynamic buffer management scheme for a data communications device. With per-flow dynamic buffer limiting, the header information for each packet is mapped into an entry in a flow table, with a separate flow table provided for each output queue. Each flow table entry maintains a buffer count for the packets currently in the queue for each flow. On each packet enqueuing action, a dynamic buffer limit is computed for the flow and compared against the buffer count already used by the flow to make a mark, drop, or enqueue decision. A packet in a flow is dropped or marked if the buffer count is above the limit. Otherwise, the packet is enqueued and the buffer count incremented by the amount used by the newly-enqueued packet. The scheme operates independently of packet data rate and flow behavior, providing means for rapidly discriminating well-behaved flows from non-well-behaved flows in order to manage buffer allocation accordingly.