Abstract: The present invention provides a method, system and computer program for ranking suspect components in a hardware design that fails verification, based on their likelihood of being actual error sources, and identifying design revisions or branches that are likely to contain actual error sources. The method is implemented as a suspect and revision ranking engine. The ranking engine involves the input of an engineer to provide an initial set of suspects or it can use the application of at least one automated debugging tool for each failure exposed by verification, and collects suspect sets returned by these tools. These tools can be based on simulation, path tracing, ATPG, BDDs, SAT, and QBF techniques. The engine applies either an analytical or statistical process on the suspects that are collected, to identify suspect components that are likely responsible for a large number of design failures.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging, A first diagnosis method enables hardware debugging by means of time abstraction. A second-diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: The present invention provides a system, method and computer program for determining constraint errors in hardware design debugging. The invention may be included as part of a complete verification solution. The method involves applying a diagnostic technique such that under-constrained problems are identified by adding a model-free error suspect or error candidate on the primary input signals (or other signals where constraints or stimuli are usually added). The present invention also provides a system, method and computer program that enables hardware design correction, consisting of the use of generating correction waveforms for identifying one or more corrections at the gate level and/or logic level of the hardware design. A number of different diagnostic techniques can be used in this way for example, include simulation-based techniques, BDD-based techniques, SAT-based techniques and path tracing.

Abstract: A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide.

Abstract: A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.

Abstract: A method of optimizing a design is disclosed, wherein a target element contributing to an undesirable characteristic in an original netlist is modified to create a modified netlist. A set of test vectors identifying differences between the original netlist and the modified netlist is identified and used to identify a set of corrections. In one disclosed embodiment, the set of corrections is identified by using an error correction algorithm. Each correction of the set of corrections, when applied to the modified netlist, results in a corrected netlist logically the same as the original netlist. One of the corrections is selected that improves the error characteristic of the original netlist. A final equivalency verification is performed as necessary.