Abstract: An optical detection device having a light detection device and a light emission device is arranged such that the light detection side of the light detection device is optically coupled to a light emission side of a light source array of the light emission device via an examination region. The light detection device generates an electrical signal n response to light that reaches the light detection side. The light source array includes a plurality of separately actuatable electric light sources which are arranged in a matrix structure or two dimensional geometric arrangement. The object to be examined can be arranged in a desired fashion, and the light emitted by the light sources radiates via the examination region on the light detection side of the light detection device. An optical reduction is system is arranged in the beam path from the light emission side to the examination region and is configured to demagnify the light pattern which is emitted by the light sources.

Abstract: A semiconductor device for emitting electromagnetic radiation, and to a method of producing the same, which can be used as a semiconductor-based, structured light source. The semiconductor device comprises a layer stack structure composed of an n-doped layer, an active layer and a p-doped layer, as well as a connection structure comprising conductor layers and at least one insulator layer, the conductor layers being arranged, parallel to and spaced apart from one another, along a first direction that is parallel to the active layer of the layer stack structure, and at least one insulator layer being arranged between at least two conductor layers, one or more conductor layers being electrically connected to the p-doped layer of the layer stack structure.

Abstract: An optoelectronic semiconductor chip and a method for manufacturing a semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a plurality of fins and a current expansion layer for common contacting of at least some of the fins, wherein each fin includes two side surfaces arranged opposite one another and an active region arranged on each of the side surfaces, wherein the plurality of fins include inner fins and outer fins having an adjacent fin only on one side, and wherein the current expansion layer is in direct contact with the inner fins on their outside.

Abstract: An optical detection device having a light detection device and a light emission device is arranged such that the light detection side of the light detection device is optically coupled to a light emission side of a light source array of the light emission device via an examination region. The light detection device generates an electrical signal n response to light that reaches the light detection side. The light source array includes a plurality of separately actuatable electric light sources which are arranged in a matrix structure or two dimensional geometric arrangement. The object to be examined can be arranged in a desired fashion, and the light emitted by the light sources radiates via the examination region on the light detection side of the light detection device. An optical reduction is system is arranged in the beam path from the light emission side to the examination region and is configured to demagnify the light pattern which is emitted by the light sources.

Abstract: An optoelectronic semiconductor chip and a method for manufacturing a semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a plurality of fins and a current expansion layer for common contacting of at least some of the fins, wherein each fin includes two side surfaces arranged opposite one another and an active region arranged on each of the side surfaces, wherein the plurality of fins include inner fins and outer fins having an adjacent fin only on one side, and wherein the current expansion layer is in direct contact with the inner fins on their outside.

Abstract: The invention relates to a light emitting device comprising a light source array which comprises a plurality of separately electrically controllable electric light sources which are arranged in a matrix structure or any other defined geometrical arrangement. Advantageously, the pixel pitch of the light source array is less than (500) nanometer. The invention further relates to an optical detection device comprising a light detection device, which is arranged for producing an electrical signal in response to light reaching a light detection side of the light detection device, and to a method for operating such an optical detection device. The invention further relates to a computer program with program coding means arranged for performing such a method.

Abstract: The invention relates to a light emitting device comprising a light source array which comprises a plurality of separately electrically controllable electric light sources which are arranged in a matrix structure or any other defined geometrical arrangement. Advantageously, the pixel pitch of the light source array is less than (500) nanometer. The invention further relates to an optical detection device comprising a light detection device, which is arranged for producing an electrical signal in response to light reaching a light detection side of the light detection device, and to a method for operating such an optical detection device. The invention further relates to a computer program with program coding means arranged for performing such a method.

Abstract: An optoelectronic semiconductor chip includes a number active regions that are arranged at a distance from each other and a substrate that is arranged on an underside of the active regions. One of the active regions has a main extension direction. The active region has a core region that is formed using a first semiconductor material. The active region has an active layer that covers the core region at least in directions perpendicular to the main extension direction of the active region. The active region has a cover layer that is formed using a second semiconductor material and covers the active layer at least in directions perpendicular to the main extension direction of the active region.

Abstract: An optoelectronic semiconductor chip includes a number active regions that are arranged at a distance from each other and a substrate that is arranged on an underside of the active regions. One of the active regions has a main extension direction. The active region has a core region that is formed using a first semiconductor material. The active region has an active layer that covers the core region at least in directions perpendicular to the main extension direction of the active region. The active region has a cover layer that is formed using a second semiconductor material and covers the active layer at least in directions perpendicular to the main extension direction of the active region.

Abstract: A method of manufacturing of a semi-conductor element, comprising the following steps: providing a substrate, the substrate having a surface, the surface being partially coated with a coating and having at least one uncoated area, and growing a truncated pyramid of gallium nitride on the uncoated area, wherein the method comprises the following step: growing at least one gallium nitride column on the truncated pyramid.

Abstract: Disclosed is an apparatus for measuring a parameter in a borehole penetrating the earth. The apparatus includes a sensor configured to be disposed in the borehole and having a piezo-resistor fabricated from a semiconductor on an insulator wherein a portion of the semiconductor is etched to the insulator to form the piezo-resistor, the piezo-resistor being responsive to the parameter.

Abstract: A method of manufacturing of a semi-conductor element, comprising the following steps: providing a substrate, the substrate having a surface, the surface being partially coated with a coating and having at least one uncoated area, and growing a truncated pyramid of gallium nitride on the uncoated area, wherein the method comprises the following step: growing at least one gallium nitride column on the truncated pyramid.

Abstract: A device for conducting heat from a source to a sink is provided that, in one embodiment, includes a thermoelectric element coupled to a substrate via sintered material that includes nano and/or micro particles. In one aspect, the sintered material includes silver particles and in another aspect the sintered material also includes an additive to control the coefficient of thermal expansion of the sintered material.

Abstract: A method of attaching members is provided. In one aspect, the method includes placing a bonding material comprising at least one of silver micro particles)and silver nano particles on a surface of a first member; placing the first member with the surface of the first member having the bonding material thereon on a surface of a second member; heating the bonding material to a selected temperature while applying a selected pressure on at least one of the first member and second member for a selected time period to sinter the bonding material to attach the first member to the second member.

Abstract: A component has an active layer, barrier layers and, if appropriate, a buffer layer and at least one of these layers contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTe/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate of GaAs, matching with low electrical resistance is achieved between the III-V materials and the II-VI materials by means of a pseudo-graded buffer layer including a beryllium-containing chalcogenide.

Abstract: A II-VI semiconductor component is produced with an active layer sequence having at least one II-VI semiconductor layer containing Se and/or S on a substrate. First, an Se-free II-VI interlayer based on BeTe is grown epitaxially on the substrate in an essentially Se-free and S-free first epitaxy chamber. The active layer sequence is then grown epitaxially on the Se-free II-VI semiconductor layer.

Abstract: The invention relates to a II-VI semiconductor component in which, within a series of layers, there is provided at least one junction between a semiconductor layer containing BeTe and a semiconductor layer containing Se. A boundary layer between the semiconductor layer containing BeTe and the semiconductor layer containing Se is prepared in such a way that it forms a Be—Se configuration.

Abstract: A component has an active layer, barrier layers and, if appropriate, a buffer layer and at least one of these layers contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTe/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate of GaAs, matching with low electrical resistance is achieved between the III-v materials and the II-VI materials by means of a pseudo-graded buffer layer including a beryllium-containing chalcogenide.

Abstract: Component having an active layer (4), barrier layers (3, 5), and, if appropriate, a buffer layer (2), of which layers at least one contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTE/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate (1) of Gaps, matching with low electrical resistance is achieved between the III-V materials and the II-VI materials by means of a pseudo-graded buffer layer (2) including a beryllium-containing chalcogenide.