Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Abstract: A method for obtaining mask and source patterns for printing integrated circuit patterns includes providing initial representations of a plurality of mask and source patterns. The method identifies long-range and short-range factors in the representations of the plurality of mask and source patterns, and provides a plurality of clips including a specified number of mask patterns. Short-range factors having overlapping ranges for each of the clips are specified. The method includes determining an initial processing priority for the plurality of clips, and determining a patterning relationship between integrated circuit patterns and the mask and source patterns. A primary objective is determined which expresses the printability of the integrated circuit patterns in terms of the patterning relationship.

Abstract: A method for obtaining mask and source patterns for printing integrated circuit patterns includes providing initial representations of a plurality of mask and source patterns. The method identifies long-range and short-range factors in the representations of the plurality of mask and source patterns, and provides a plurality of clips including a specified number of mask patterns. Short-range factors having overlapping ranges for each of the clips are specified. The method includes determining an initial processing priority for the plurality of clips, and determining a patterning relationship between integrated circuit patterns and the mask and source patterns. A primary objective is determined which expresses the printability of the integrated circuit patterns in terms of the patterning relationship.