Abstract: Embodiments of the invention include a computer-implemented method for detecting anomalies in non-stationary data in a network of computing entities. The method collects non-stationary data in the network and classifies the non-stationary data according to a non-Markovian, stateful classification, based on an inference model. Anomalies can then be detected, based on the classified data. The non-Markovian, stateful process allows anomaly detection even when no a priori knowledge of anomaly signatures or malicious entities exists. Anomalies can be detected in real time (e.g., at speeds of 10-100 Gbps) and the network data variability can be addressed by implementing a detection pipeline to adapt to changes in traffic behavior through online learning and retain memory of past behaviors. A two-stage scheme can be relied upon, which involves a supervised model coupled with an unsupervised model.

Abstract: A method for dynamically selecting a size of a memory access may be provided. The method comprises accessing blocks having a variable number of consecutive cache lines, maintaining a vector with entries of past utilizations for each block size, and adapting said block size before a next access to the blocks.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.

Abstract: Embodiments of the invention include a computer-implemented method of processor branch prediction. This method aims at training a machine-learning model of processor branch behavior while a processing unit executes computer instructions. Such instructions include branch instructions, load instructions and store instructions. The load instructions and the store instructions cause a control unit of the processing unit to load data from a memory into processor registers and store data from the processor registers to the memory, respectively. Basically, the training of the model involves, for each of N branch instructions (N>2) encountered whilst the processing unit executes said branch instructions: identifying a next branch instruction; and feeding the machine-learning model with carefully chosen inputs.