Abstract: A device for reducing irrational-base codes to a minimal form, comprising "n" identical functional cells whereof each Bth cell incorporates a flip-flop with a count input and an AND convolution element intended to evaluate the possibility of performing the operation of convoluting the (B-1)th and (B-p-1)th code digits to the Bth code digit. One of the inputs of the AND convolution element is connected to an inverting output of the flip-flop whose direct output serves as an information output of the Bth functional cell. The flip-flop has its set, reset and count inputs connected to an information input, a convolution set input and an inversion signal input, respectively, of the Bth functional cell, the inversion signal input being connected to an information output of the (B-1)th functional cell. The remaining inputs of the AND convolution element are a first convolution signal input, a second convolution signal input and a convolution control input of the Bth functional cell.

Abstract: A Fibonacci p-code parallel adder comprises an augend register and an addend register having outputs coupled to the inputs of an end-of-addition detector and a monitoring unit and to the data inputs of a logic unit which comprises n rewrite AND gates. The AND gates have their inputs coupled to the complement and true outputs respectively of the augend and addend registers so as to provide for analyzing the condition of the flip-flips of the registers, and have their outputs coupled to the set inputs of the bit positions of the augend register and, via a delay unit, to the reset inputs of the bit position of the addend register, which provides for transfer of a 1 from the ith bit position of the addend register to the ith bit position of the augend register containing a 0. A Fibonnaci p-code minimizing unit has its inputs coupled to the outputs of the augend and addend registers, and has its outputs coupled to the normalize signal input of the augend register.