Abstract: Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

Abstract: Techniques to perform forward error correction for an electrical backplane are described.

Abstract: Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Apparatus and systems, as well as methods and articles, encode a data word into an unequal error protection (UEP) codeword and transmit first and second portions of the UEP codeword associated with first and second protection levels across first and second sub-channel subsets associated with first and second error probabilities and a multi-channel communications link, respectively.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.

Abstract: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bh is over GF(2) including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector v1 component-wise in GF(q) to produce a column vector v2, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector v2 in GF(2) to produce a column vector v3.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Abstract: Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes.

Abstract: Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes.

Abstract: Apparatus and systems, as well as methods and articles, may operate to encode a data word into an unequal error protection (UEP) codeword and to transmit first and second portions of the UEP codeword associated with first and second protection levels across first and second sub-channel subsets associated with first and second error probabilities and a multi-channel communications link, respectively.

Abstract: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bh is over GF(2) including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector v1 component-wise in GF(q) to produce a column vector v2, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector v2 in GF(2) to produce a column vector v3.

Abstract: A method and apparatus are provided for a coding process of a communication signal. A 3-stripes parity-check matrix is generated from a parity-check matrix of a Gilbert low density parity-check code, where the parity-check matrix of the Gilbert low density parity-check code has a first stripe containing identity matrices and a second stripe containing cyclic permutation matrices. A third stripe is added to form a 3-stripes parity-check matrix, which may be applied to the coding process of information in a communication channel.

Abstract: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.

Abstract: The present invention provides a method and system for change control management of schema definition objects across disparate systems. A determination is made when a proposed change associated with an object is made; an impact analysis is performed on the proposed change; the change is implemented when the impact analysis indicates that there is no impact on, other system stakeholders otherwise: a change object based on the proposed change is created, voting rights are allocated to users based on the impact analysis; and the proposed change is accepted or canceled in response to the voting. Change control contracts may be associated with the objects. The contracts may be customized to establish change management rules for and enterprise and to specialize rules for certain objects or branches of a Content Class tree corresponding to a department or a discipline. The access to changing the contracts may also be limited to help ensure that the contracts are not bypassed.