Patents by Inventor Andrei Josiek

Andrei Josiek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230038354
    Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field including transistor cells, and an edge termination region laterally surrounding the cell field. Each transistor cell includes a drift region of a first conductivity type, a first body region of a second conductivity type on the drift region, a source region of the first conductivity type on the first body region and a gate electrode. The transistor device further includes an elongate source contact having opposing first and second distal ends, the elongate source contact being in contact with the source region, and a second body region of the second conductivity type positioned in the semiconductor substrate. The second body region has a lateral extent such that it is spaced part from the second distal end of the elongate source contact and extends laterally beyond the first distal end of the elongate source contact.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Inventors: Alessandro Ferrara, Andrei Josiek, Matthias Kroenke, Stefan Tegen
  • Publication number: 20230006059
    Abstract: A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.
    Type: Application
    Filed: June 23, 2022
    Publication date: January 5, 2023
    Inventors: Stefan Tegen, Alessandro Ferrara, Franz Hirler, Andrei Josiek, Matthias Kroenke
  • Patent number: 8138538
    Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: March 20, 2012
    Assignee: Qimonda AG
    Inventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
  • Publication number: 20100090264
    Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 15, 2010
    Applicant: Qimonda AG
    Inventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
  • Publication number: 20080256325
    Abstract: A device includes an input for an N-bit data word. A circuit is adapted to map the N-bit data word to a physical M-bit memory data word by means of a mapping rule. The mapping rule includes a quantity of values of possible physical M-bit memory data words the mean number of first physical bit values of which is smaller than N/2. The circuit also includes output for the physical M-bit memory data word. Memory cells are couplable to the output.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventor: Andrei Josiek
  • Publication number: 20070148893
    Abstract: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a resist layer are provided on the substrate surface, where the portions of the resist layer are arranged in a pattern of lines or segments of lines extending in a second direction, and the second direction intersects the first direction. The portions of the resist layer have a thickness d, the thickness d being measured perpendicularly with respect to the substrate surface. A tilted ion implantation step is then performed.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Andrei Josiek, Georg Erley, Juergen Faul, Martin Popp