Abstract: A technique is provided that dynamically controls the speed at which a mobile device user can use funds. More specifically, the technique provides a lockout mechanism, which temporarily prevents the mobile device user from accessing and thus spending the funds.

Abstract: A technique is provided that dynamically controls the speed at which a mobile device user can use funds. More specifically, the technique provides a lockout mechanism, which temporarily prevents the mobile device user from accessing and thus spending the funds.

Abstract: In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Abstract: A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.

Abstract: A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

Abstract: A technique is provided that dynamically controls the speed at which a mobile device user can use funds. More specifically, the technique provides a lockout mechanism, which temporarily prevents the mobile device user from accessing and thus spending the funds.

Abstract: The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied.

Abstract: In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Abstract: A method of controlling access by a master to a peripheral includes receiving one or more interrupt priority levels from one or more interrupt controllers associated with the peripheral, comparing the one or more interrupt priority level with respective one or more pre-established interrupt access levels to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on at least the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including one or more masters, one or more peripherals, and an access control circuitry including one or more interrupt controllers associated with the one or more peripherals. The access control circuitry is arranged to perform a method of controlling access by a master of the one or more masters to a peripheral of the one or more peripherals.