Patents by Inventor Andrei Mihai Hagiescu Miriste
Andrei Mihai Hagiescu Miriste has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11899746Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).Type: GrantFiled: December 23, 2021Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Martin Langhammer, Andrei-Mihai Hagiescu-Miriste
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Publication number: 20230418573Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.Type: ApplicationFiled: September 13, 2023Publication date: December 28, 2023Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
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Patent number: 11379242Abstract: An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline. Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.Type: GrantFiled: June 29, 2017Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Andrei Mihai Hagiescu Miriste, Byron Sinclair, Joseph Garvey
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Publication number: 20220114236Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Inventors: Martin Langhammer, Andrei-Mihai Hagiescu-Miriste
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Patent number: 11216532Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).Type: GrantFiled: March 29, 2019Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Martin Langhammer, Andrei-Mihai Hagiescu-Miriste
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Publication number: 20210349702Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.Type: ApplicationFiled: May 24, 2021Publication date: November 11, 2021Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
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Patent number: 11016742Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.Type: GrantFiled: June 24, 2015Date of Patent: May 25, 2021Assignee: Altera CorporationInventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
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Patent number: 10437743Abstract: The present embodiments relate to interface circuitry between a serial interface circuit and an array of processing elements in an integrated circuit. The interface circuitry may include a daisy chain of feeder circuits and a daisy chain of drain circuits. If desired, the interface circuitry may include multiple daisy chains of feeder circuits and/or multiple daisy chains of drain circuits. These multiple daisy chains of feeder circuits and drains circuits may be coupled in parallel, respectively. In some embodiments, the interface circuitry may include synchronization circuitry that is coupled between the daisy chains of drain circuits and the serial interface circuit. Pipeline register stages between feeder circuits and/or between drain circuits may enable the placement of the feeder circuits and/or the drain circuits spatially close to the processing elements of the array of processing elements.Type: GrantFiled: April 1, 2016Date of Patent: October 8, 2019Assignee: Altera CorporationInventors: Davor Capalija, Andrei Mihai Hagiescu Miriste, John Stuart Freeman, Alan Baker
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Publication number: 20190228051Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Martin Langhammer, Andrei-Mihai Hagiescu-Miriste
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Patent number: 10339201Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.Type: GrantFiled: August 13, 2018Date of Patent: July 2, 2019Assignee: Altera CorporationInventors: Andrew Chaang Ling, Davor Capalija, Tomasz Sebastian Czajkowski, Andrei Mihai Hagiescu Miriste
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Patent number: 10303831Abstract: A method for designing a system on a target device includes generating a scheduled netlist and a hardware description language (HDL) of the system from a computer language description of the system. An area report is generated prior to HDL compilation, based on estimates from the scheduled netlist, that identifies resources from the target device required to implement portions of the computer language description of the system.Type: GrantFiled: December 4, 2015Date of Patent: May 28, 2019Assignee: Altera CorporationInventors: Maryam Sadooghi-Alvandi, Andrei Mihai Hagiescu Miriste, Alan Baker, Dmitry Nikolai Denisenko
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Publication number: 20190004804Abstract: An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline. Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Andrei Mihai Hagiescu Miriste, Byron Sinclair, Joseph Garvey
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Patent number: 10049082Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.Type: GrantFiled: September 15, 2016Date of Patent: August 14, 2018Assignee: ALTERA CORPORATIONInventors: Andrew Chaang Ling, Davor Capalija, Tomasz Sebastian Czajkowski, Andrei Mihai Hagiescu Miriste
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Publication number: 20180074996Abstract: Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Andrew Chaang Ling, Davor Capalija, Tomasz Sebastian Czajkowski, Andrei Mihai Hagiescu Miriste
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Publication number: 20160378441Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Inventors: Alan Baker, Andrew Chaang Ling, Andrei Mihai Hagiescu Miriste
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Patent number: 9529950Abstract: Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL.Type: GrantFiled: March 18, 2015Date of Patent: December 27, 2016Assignee: Altera CorporationInventors: Maryam Sadooghi-Alvandi, Dmitry Nikolai Denisenko, Andrei Mihai Hagiescu Miriste