Abstract: Disclosed herein is a method that directs the components and signal detection path of a binary data bit decision mechanism used to obtain the bit error rate of the bit stream of an incoming or applied data signal to generate an eye diagram. More precisely, components such as the trigger-to-data delay adjustment to generate a delayed trigger pulse, the variable decision threshold setting, the bit detection flip flop in the input signal path to perform bit sampling, the total bits counter as a window size counter and the error counter to accumulate the occurrences when incoming signal exceeds a specified voltage threshold voltage range for a instance in time are used to implement the functionality required to generate the eye diagram.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.

Abstract: Disclosed herein is a method and apparatus used to create variable delay output from a high-speed trigger input signal. A variable delay generation circuit includes a preconditioning circuit, operative to provide a preconditioned signal in response to an input signal. At least one delay tap path is coupled to the preconditioned signal, and is operative to provide a delayed version of the preconditioned signal. The delay path includes a delay element and a scaling circuit. A summing circuit is coupled to the at least one delay tap path and preconditioned signal, and is operative to provide an output signal exhibiting variable delay characteristics in response to the preconditioned signal and the delayed version of the preconditioned signal. The delayed version of the preconditioned signal may be provided by an elongated signal trace between the preconditioning circuit and the delay tap path.

Abstract: Sub-sampled signals are compared to determine time delay, calibration of delay elements, and other precise time domain measurements, based on properties of aliased signals produced by the sub-sampling. In one embodiment, flip-flops sub-sample an input signal and a delayed signal. A counter measures time delay between edges in the sub-sampled input and sub-sampled delayed signal. The time delay is determined and averaged over a measurement window, and then scaled to determine an amount of delay of the delayed signal. Means to calibrate a delay element inside a measurement device (e.g., Bit Error Ratio Tester), utilizing sub-sampling techniques to achieve precise measurements very quickly and without the need for factory calibration.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.

Abstract: Disclosed herein is a method and apparatus used to create variable delay output from a high-speed trigger input signal. A variable delay generation circuit includes a preconditioning circuit, operative to provide a preconditioned signal in response to an input signal. At least one delay tap path is coupled to the preconditioned signal, and is operative to provide a delayed version of the preconditioned signal. The delay path includes a delay element and a scaling circuit. A summing circuit is coupled to the at least one delay tap path and preconditioned signal, and is operative to provide an output signal exhibiting variable delay characteristics in response to the preconditioned signal and the delayed version of the preconditioned signal. The delayed version of the preconditioned signal may be provided by an elongated signal trace between the preconditioning circuit and the delay tap path.

Abstract: A differential signal reception device and method for supporting variable threshold levels. The device flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltage. The device further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: Disclosed herein is a method that directs the components and signal detection path of a binary data bit decision mechanism used to obtain the bit error rate of the bit stream of an incoming or applied data signal to generate an eye diagram. More precisely, components such as the trigger-to-data delay adjustment to generate a delayed trigger pulse, the variable decision threshold setting, the bit detection flip flop in the input signal path to perform bit sampling, the total bits counter as a window size counter and the error counter to accumulate the occurrences when incoming signal exceeds a specified voltage threshold voltage range for a instance in time are used to implement the functionality required to generate the eye diagram.

Abstract: The present invention relates to a differential signal reception device and method for supporting variable threshold levels. The present invention flexibly makes an input to the decision circuit appear to an outside driving circuit as if the decision circuit were a purpose-built input network supporting a fixed impedance input into either a floating or fixed DC termination voltag 1844X The present invention further allows the internal decision process to support a variable threshold level when deciding logical 1/0 values and to attenuate the users input signal range for the purpose of making sure the range of the user's signals do not exceed the operating range of readily available decision circuit (limiting amplifier) integrated circuits.

Abstract: Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.