Abstract: A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

Abstract: A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

Abstract: Apparatus, systems, and methods are provided for processing integrated circuit chip design. A three-dimensional Monte Carlo random-walk process may be applied to a cell in a hierarchical description of the layout of the chip to extract information regarding the cell. The information may include coupling resistance, capacitance, inductance, or combinations thereof. A neighborhood of the cell may be built and data correlated to the neighborhood may be stored. Such a technique may be applied from a bottom level to a top level of the hierarchical description of the chip layout.

Abstract: Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state.