Abstract: According to an aspect of an embodiment, a method of array source code partitioning and topology determination may include determining an optimum topology of an array of field programmable gate array (FPGA) devices based on a processing specification. The method may include automatically performing the best-effort partitioning on a default topology of the array of FPGA devices. The method may include partitioning parallel and serial source code among the FPGA devices mapped into optimum topology or the default topology. The method may include mapping a virtual topology onto a fixed physical topology of the array of FPGA devices. The method may include presenting computing resources of the array of FPGA devices to a host or to an entire application as a larger FPGA or as software-defined computing resources.

Abstract: According to an aspect of an embodiment, a method of array source code partitioning and topology determination may include determining an optimum topology of an array of field programmable gate array (FPGA) devices based on a processing specification. The method may include automatically performing the best-effort partitioning on a default topology of the array of FPGA devices. The method may include partitioning parallel and serial source code among the FPGA devices mapped into optimum topology or the default topology. The method may include mapping a virtual topology onto a fixed physical topology of the array of FPGA devices. The method may include presenting computing resources of the array of FPGA devices to a host or to an entire application as a larger FPGA or as software-defined computing resources.

Abstract: A forwarding plane comprising a scalable array of field programmable gate array (FPGA) devices, a memory bank, FPGA data and transport network ports, and an array interconnect. The scalable array is configured to execute a networking application source code partitioned as computing elements executed by the FPGA devices with a uniform global memory address space. The memory bank includes an allocated portion of the FPGA devices addressable by the address space. The ports are coupled to data networks and include ingress ports configured to receive traffic and egress ports configured to transmit traffic. The array interconnect is configured to forward the traffic from the ingress ports to the egress ports, choose cell sizes of data cells that encapsulate payload data units of the traffic, control latency between the FPGA devices based on the chosen cell sizes; and enable utilization of the memory bank for buffering of the traffic.

Abstract: A forwarding plane comprising a scalable array of field programmable gate array (FPGA) devices, a memory bank, FPGA data and transport network ports, and an array interconnect. The scalable array is configured to execute a networking application source code partitioned as computing elements executed by the FPGA devices with a uniform global memory address space. The memory bank includes an allocated portion of the FPGA devices addressable by the address space. The ports are coupled to data networks and include ingress ports configured to receive traffic and egress ports configured to transmit traffic. The array interconnect is configured to forward the traffic from the ingress ports to the egress ports, choose cell sizes of data cells that encapsulate payload data units of the traffic, control latency between the FPGA devices based on the chosen cell sizes; and enable utilization of the memory bank for buffering of the traffic.

Abstract: An array of field programmable gate array (FPGA) devices configured for execution of a source code. The array includes two or more FPGA devices, a host processor, and a host interface logic. The FPGA devices are configured to execute a parallelized portion of the source code partitioned among the FPGA devices based on data rates of computing elements of the source code, computational performance of the FPGA devices, the input/output (I/O) bandwidth of the FPGA devices. The FPGA devices include a memory bank addressable by a global memory address space for the array and an array interconnect that enables the computing elements executed by each of the FPGA devices to be programmed with a uniform address space of a global memory of the array and utilization of the global memory by the FPGA devices. The host interface logic connects the host processor with one of the FPGA devices.