Patents by Inventor ANDREI VALENTIN
ANDREI VALENTIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11676239Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, Jr., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
-
Publication number: 20210374897Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.Type: ApplicationFiled: June 3, 2021Publication date: December 2, 2021Applicant: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
-
Patent number: 11113784Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.Type: GrantFiled: October 6, 2020Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, Jr., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
-
Publication number: 20210035258Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.Type: ApplicationFiled: October 6, 2020Publication date: February 4, 2021Applicant: Intel CorporationInventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
-
Publication number: 20200293456Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: MURALI RAMADOSS, VIKRANTH VEMULAPALLI, NIRAN COORAY, WILLIAM B. SADLER, JONATHAN D. PEARCE, MARIAN ALIN PETRE, BEN ASHBAUGH, ELMOUSTAPHA OULD-AHMED-VALL, NICOLAS GALOPPO VON BORRIES, ALTUG KOKER, ARAVINDH ANANTARAMAN, SUBRAMANIAM MAIYURAN, VARGHESE GEORGE, SUNGYE KIM, ANDREI VALENTIN
-
Patent number: 10547458Abstract: Systems and techniques are described herein for managing and negotiating SSL certificates as part of a handshake between a client computing device and a website hosting infrastructure. Certificates for a website are stored in a common storage and are lazy-loaded into cache memory when the website is requested by a client. Certificates are served by the hosting infrastructure responsive to a handshake request from a client by determining if a certificate for a hostname in the handshake request is in cache memory. When available, a cached certificate is served. When a cached certificate for the hostname is unavailable, a certificate is retrieved from the common storage, placed in cache memory, and served. OCSP stapling data is lazy-loaded and served also from the cache memory. Hence, a certificate is available immediately upon deployment, without costly reconfiguration of the hosting platform to accommodate new certificates and new hostnames.Type: GrantFiled: February 6, 2018Date of Patent: January 28, 2020Assignee: Adobe Inc.Inventors: Alexandru-Cristian Dobre, Raluca Voinescu, Paul Alexandru Chirita, Edvin Ali, Bogdan Ionita, Andrei-Valentin Duca
-
Publication number: 20190245700Abstract: Systems and techniques are described herein for managing and negotiating SSL certificates as part of a handshake between a client computing device and a website hosting infrastructure. Certificates for a website are stored in a common storage and are lazy-loaded into cache memory when the website is requested by a client. Certificates are served by the hosting infrastructure responsive to a handshake request from a client by determining if a certificate for a hostname in the handshake request is in cache memory. When available, a cached certificate is served. When a cached certificate for the hostname is unavailable, a certificate is retrieved from the common storage, placed in cache memory, and served. OCSP stapling data is lazy-loaded and served also from the cache memory. Hence, a certificate is available immediately upon deployment, without costly reconfiguration of the hosting platform to accommodate new certificates and new hostnames.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Applicant: Adobe Inc.Inventors: Alexandru-Cristian Dobre, Raluca Voinescu, Paul Alexandru Chirita, Edvin Ali, Bogdan Ionita, Andrei-Valentin Duca