Patents by Inventor Andrej A. Zolotykh
Andrej A. Zolotykh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120278783Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.Type: ApplicationFiled: July 9, 2012Publication date: November 1, 2012Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 8160242Abstract: An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.Type: GrantFiled: October 7, 2008Date of Patent: April 17, 2012Assignee: LSI CorporationInventors: Mikhail Grinchuk, Anatoli Bolotov, Lay D. Ivanovic, Andrej A. Zolotykh, Alexei V. Galatenko
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Publication number: 20110258587Abstract: A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: LSI CORPORATIONInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Publication number: 20100086127Abstract: An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.Type: ApplicationFiled: October 7, 2008Publication date: April 8, 2010Inventors: Mikhail Grinchuk, Anatoli Bolotov, Lav D. Ivanovic, Andrej A. Zolotykh, Alexei V. Galatenko
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Patent number: 7568175Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.Type: GrantFiled: June 1, 2007Date of Patent: July 28, 2009Assignee: LSI CorporationInventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko, Ilya V. Lyalin
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Publication number: 20090187873Abstract: A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.Type: ApplicationFiled: January 17, 2008Publication date: July 23, 2009Applicant: LSI CorporationInventors: Andrey Nikitin, Ranko Scepanovic, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto, Andrej Zolotykh, Ivan Pavisic, Sandeep Bhutani, Aiguo Lu, Ilya Lyalin
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Patent number: 7496870Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.Type: GrantFiled: October 20, 2006Date of Patent: February 24, 2009Assignee: LSI CorporationInventors: Iliya V. Lyalin, Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko
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Patent number: 7398486Abstract: The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters.Type: GrantFiled: March 17, 2004Date of Patent: July 8, 2008Assignee: LSI CorporationInventors: Alexei V. Galatenko, Elyar E. Gasanov, Andrej A. Zolotykh
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Publication number: 20070234255Abstract: A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.Type: ApplicationFiled: June 1, 2007Publication date: October 4, 2007Applicant: LSI Logic CorporationInventors: Andrej Zolotykh, Elyar Gasanov, Alexei Galatenko, Ilya Lyalin
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Patent number: 7257791Abstract: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.Type: GrantFiled: November 19, 2004Date of Patent: August 14, 2007Assignee: LSI CorporationInventors: Alexei V. Galatenko, Elyar E. Gasanov, Andrej A. Zolotykh, Iliya V. Lyalin
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Patent number: 7246336Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.Type: GrantFiled: December 3, 2004Date of Patent: July 17, 2007Assignee: LSI CorporationInventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko, Ilya V. Lyalin
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Publication number: 20070050744Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.Type: ApplicationFiled: October 20, 2006Publication date: March 1, 2007Applicant: LSI Logic CorporationInventors: Iliya Lyalin, Andrej Zolotykh, Elyar Gasanov, Alexei Galatenko
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Patent number: 7146591Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.Type: GrantFiled: November 19, 2004Date of Patent: December 5, 2006Assignee: LSI Logic CorporationInventors: Iliya V. Lyalin, Andrej A. Zolotykh, Elyar E. Gasanov, Alexei V. Galatenko
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Patent number: 7111267Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.Type: GrantFiled: August 27, 2004Date of Patent: September 19, 2006Assignee: LSI Logic CorporationInventors: Elyar E. Gasanov, Iliya V. Lyalin, Alexei V. Galatenko, Andrej A. Zolotykh
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Publication number: 20060123369Abstract: A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.Type: ApplicationFiled: December 3, 2004Publication date: June 8, 2006Applicant: LSI Logic CorporationInventors: Andrej Zolotykh, Elyar Gasanov, Alexei Galatenko, Ilya Lyalin
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Publication number: 20060112363Abstract: Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.Type: ApplicationFiled: November 19, 2004Publication date: May 25, 2006Applicant: LSI Logic CorporationInventors: Alexei Galatenko, Elyar Gasanov, Andrej Zolotykh, Ilya Lyalin
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Publication number: 20060112361Abstract: The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.Type: ApplicationFiled: November 19, 2004Publication date: May 25, 2006Applicant: LSI Logic CorporationInventors: Iliya Lyalin, Andrej Zolotykh, Elyar Gasanov, Alexei Galatenko
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Publication number: 20060048087Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.Type: ApplicationFiled: August 27, 2004Publication date: March 2, 2006Applicant: LSI Logic CorporationInventors: Elyar Gasanov, Iliya Lyalin, Alexei Galatenko, Andrej Zolotykh
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Publication number: 20050210422Abstract: The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Inventors: Alexei Galatenko, Elyar Gasanov, Andrej Zolotykh
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Patent number: 6868536Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.Type: GrantFiled: November 19, 2002Date of Patent: March 15, 2005Assignee: LSI Logic CorporationInventors: Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu