Abstract: A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

Abstract: A system and method for a radar system are provided. The radar system includes a leader radar device that includes a first clock generation circuit configured to generate a first clock signal, and a first transmitter and receiver configured to transmit and receive radar signals using a first local oscillator signal. The system includes a follower radar device. The follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device. The follower radar device includes a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled, and a second transmitter and receiver configured to transmit and receive first radar signals.

Abstract: A layered architecture for managing health of the electronic system comprises a plurality of health subsystems. Health subsystems receive health information from health monitors coupled to respective components of the electronic system and provide the health information to another health subsystem. Based on the received health information, the other health subsystem uses predictive data analytics to determine a health condition of the electronic system and update a health policy based on the predictive data analytics to improve prediction of the health condition of the electronic system.

Abstract: An event manager for filtering safety and security events of a system including an event sequence list including predetermined event sequences in which each sequence includes at least one event identifier identifying a corresponding one of multiple monitored events, an event sequence array that stores a received event sequence in response to received event notifications, and a controller that stores an event identifier into the event sequence array and that determines whether the received event sequence matches at least one of the predetermined event sequences for determining a composite event and a response for each received event notification. The matching determination may be made with or without consideration of chronological order. A suspected composite event may be identified when multiple possible matches may exist, and a final composite event is ratified when only one match is found. An exception may be generated upon timeout of a timer.

Abstract: An architecture for monitoring, analyzing, and reacting to safety and cybersecurity events has been disclosed. In at least one embodiment, a method for processing safety and security events of a system includes requesting a reaction or escalating an effect from a first controller of the system to a second controller of the system based on a subset of available reactions for a current context of the system, constraint information, a predetermined effect-reaction policy, and the effect.

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

Abstract: A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

Abstract: A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).

Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.