Abstract: Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.

Abstract: Power control arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes an integrated circuit device comprising one or more processing cores and a power domain configured to distribute a supply voltage to the one or more processing cores. The assembly also includes a charge injection circuit coupled to the power domain of the integrated circuit device, and configured to selectively couple electric charge into the power domain to predictively offset at least portions of voltage transients in the power domain.

Abstract: Power supply architectures and enhanced power control techniques are presented herein. In one example, a system includes a plurality of power supply phases and a system processor. The system processor comprises a processing unit comprising a plurality of processing cores, a plurality of power domains configured to segregate power distribution for the processing unit into sets of the plurality of processing cores, and external connections configured to couple individual ones the plurality of power domains to individual ones of the plurality of power supply phases.

Abstract: Power supply circuitry and enhanced associated techniques are presented herein. In one example, a method includes powering a circuit with a plurality of power supply phases, and monitoring thermal properties of the plurality of power supply phases. Responsive to the thermal properties indicating at least one of the plurality of power supply phases exceeds a thermal threshold, the method includes selecting a dormant power supply phase to supplant the at least one of the plurality of power supply phases.

Abstract: Computing assemblies, such as blade servers, can be housed in rackmount systems of data centers for execution of applications for remote users. These applications can include games and other various user software. In one example, a method of operating a data processing system includes receiving requests for execution of a plurality of applications, and identifying estimated power demands for execution of each of the plurality of applications. The method also includes determining power limit properties for a plurality of computing modules capable of executing the plurality of applications, and selecting among the plurality of computing modules to execute ones of the plurality of applications based at least on the power limit properties and the estimated power demands.

Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes executing a voltage characterization service for a processing device of a computing apparatus to determine at least one supply voltage for the processing device, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus. During execution of the voltage characterization service, the method includes monitoring for operational failures of at least the processing device, and responsive to the operational failures, determining at least one resultant supply voltage.

Abstract: Power supply architectures and enhanced power control techniques are presented herein. In one example, a system includes a plurality of power supply phases and a system processor. The system processor comprises a processing unit comprising a plurality of processing cores, a plurality of power domains configured to segregate power distribution for the processing unit into sets of the plurality of processing cores, and external connections configured to couple individual ones the plurality of power domains to individual ones of the plurality of power supply phases.

Abstract: Decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, where the first circuit board is coupled to first surface of a system circuit board. The assembly includes a second circuit assembly comprising a second circuit board having decoupling capacitance for the integrated circuit device, where the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.

Abstract: Voltage control arrangements for integrated circuit devices are discussed herein. In one example, a method includes receiving an indication of one or more software elements selected for execution by an integrated circuit device, and determining a target level of a supply voltage for the integrated circuit device based on the indication. The method also includes controlling voltage regulation circuitry to adjust a present level of the supply voltage for the integrated circuit device in accordance with the target level.

Abstract: Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.

Abstract: Power control arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes an integrated circuit device comprising one or more processing cores and a power domain configured to distribute a supply voltage to the one or more processing cores. The assembly also includes a charge injection circuit coupled to the power domain of the integrated circuit device, and configured to selectively couple electric charge into the power domain to predictively offset at least portions of voltage transients in the power domain.

Abstract: Power supply circuitry and enhanced associated techniques are presented herein. In one example, a method includes powering a circuit with a plurality of power supply phases, and monitoring thermal properties of the plurality of power supply phases. Responsive to the thermal properties indicating at least one of the plurality of power supply phases exceeds a thermal threshold, the method includes selecting a dormant power supply phase to supplant the at least one of the plurality of power supply phases.

Abstract: Computing assemblies, such as blade servers, can comprise a plurality of modular computing elements coupled onto an associated circuit board assembly. Assemblies and systems having enhanced individual computing module placement and arrangement are discussed herein, as well as example systems and operations to manufacture such assemblies. In one example, a method includes executing a performance test on a plurality of computing modules to determine at least variability in power consumption across the plurality of computing modules, and binning the plurality of computing modules according to graduated levels of the variability in power consumption. The method also includes selecting from among the graduated levels for placement in an assembly of ones of the computing modules in a progressively lower power consumption arrangement with relation to an airflow of the assembly.

Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.

Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes executing a voltage characterization service for a processing device of a computing apparatus to determine at least one supply voltage for the processing device, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus. During execution of the voltage characterization service, the method includes monitoring for operational failures of at least the processing device, and responsive to the operational failures, determining at least one resultant supply voltage.

Abstract: Thermal reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In a first example, a method of operating a voltage control system for a processing device includes operating the processing device in a computing assembly at a selected performance level, the processing device supplied with at least one input voltage at a first voltage level. The method includes monitoring thermal information associated with the computing assembly, and when the thermal information indicates a temperature associated with the computing assembly exceeds a threshold temperature, adjusting the at least one input voltage level supplied to the processing device to a second voltage level lower than the first voltage level and continuing to operate the processing device at the selected performance level.

Abstract: Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes receiving a voltage characterization service over a communication interface of the computing apparatus as transferred by a deployment platform remote from the computing apparatus. The method includes executing the voltage characterization service for a processing device of the computing apparatus to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus.

Abstract: Secure voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of controlling operating voltages for a processing device includes initializing a security portion of the processing device after application of input voltages to the processing device as supplied by voltage regulation circuitry according to voltage identifiers (VIDs) established for the processing device. The method includes, in the security portion, generating adjusted input voltages based on at least the VIDs and authenticated voltage offset information stored according to a digitally signed security process, and instructing the voltage regulation circuitry to supply the adjusted input voltages to the processing device.

Abstract: Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages.

Abstract: Secure voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of controlling operating voltages for a processing device includes initializing a security portion of the processing device after application of input voltages to the processing device as supplied by voltage regulation circuitry according to voltage identifiers (VIDs) established for the processing device. The method includes, in the security portion, generating adjusted input voltages based on at least the VIDs and authenticated voltage offset information stored according to a digitally signed security process, and instructing the voltage regulation circuitry to supply the adjusted input voltages to the processing device.