Patents by Inventor Andres R. Teene

Andres R. Teene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6539509
    Abstract: A method for eliminating scan hold time failures of a scan chain. The method uses information resulting from the distribution of a clock throughout an integrated circuit. In particular, a scan chain is reordered according to the results of the distribution of the clock signal. The distribution of the clock signal provides groups of sequential circuit elements that form the scan chain. The method also includes reordering the sequential circuit elements within at least one group according to a clock skew of the clock signal within the at least one group. The method further includes ordering the groups according to a clock skew of the clock signal between the groups.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: March 25, 2003
    Assignee: LSI Logic Corporation
    Inventor: Andres R. Teene
  • Patent number: 6272668
    Abstract: A method for improving the timing performance of a standard cell ASIC layout. The method is operable at any phase of the ASIC design cycle including following the completion of layout phase placement and routing. The method compares post-layout timing values with pre-layout timing targets for each timing arc associated with each standard cell component of the ASIC design. For each timing arc, a functionally equivalent cell having higher or lower output drive is selected which optimally improves the timing slack on each timing arc. To assure that the method converges and terminates, a list of timing slack values, one for each timing arc of the ASIC design, is constructed in sorted order from worst timing slack to best timing slack. The swap method determines in order from worse timing slack to best a functionally equivalent standard cell which may be swapped to improve the timing slack on the timing arc.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: August 7, 2001
    Assignees: Hyundai Electronics America, Inc., NCR Corporation
    Inventor: Andres R. Teene
  • Patent number: 5903577
    Abstract: A method in a data processing system for identifying hazards in a circuit. Signal paths are identified in the circuit. Each signal path within the plurality of signal paths begins at a source and ends at a target and each signal path within the signal paths is one that potentially propagates a hazard. Errors are then identified in signal paths in the circuit by analyzing the timing relationships and hazard characteristics of the signals within the signal paths.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: May 11, 1999
    Assignee: LSI Logic Corporation
    Inventor: Andres R. Teene
  • Patent number: 5726997
    Abstract: Current monitoring cells are located at selected locations on power supply lines within a chip. Each cell compares the current flow at predetermined times with a reference. If the current exceeds the reference, a signal is provided indicating a fault in the chip. A flip flop in the cell is set to maintain an indication of the fault condition. In two embodiments, the cells are connected with a scan chain which is used to sequentially access the test results for each cell. A third embodiment does not include the scan chain. A current divider may be included in each cell to isolate the voltage drop of the fault sensor from the functional circuit to minimize the impact of measuring the current for fault detection purposes.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: March 10, 1998
    Inventor: Andres R. Teene
  • Patent number: 5528447
    Abstract: In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: June 18, 1996
    Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
    Inventors: Michael J. McManus, Philip W. Bullinger, Andres R. Teene, Gerald R. Haag, Hoang P. Nguyen