Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.

Abstract: Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: In various implementations of the invention, a model of an optical proximity correction process is employed to determine potential adjustments to a layout design for a mask that might resolve potential errors an image resulting from application of the mask in an optical lithographic process. In various implementations of the invention, corrected mask shapes, such as for example optical proximity corrected mask shapes, and associated printed image contours are generated through use of a model. Subsequently, the associated printed image contour and a desired printed image contour may be used to determine various edge segment adjustments to the corrected mask shapes that would realize the desired printed image contour. In various implementations of the present invention, the model for generation of the corrected mask shapes and the associated printed image contour is a square kernel model.

Abstract: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.

Abstract: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjustments facilitating resolution of the potential manufacturing fault.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments having a contrast value that exceeds a predetermined threshold.

Abstract: Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.

Abstract: A contrast-base resolution enhancing technology (RET) receives an indication of an edge fragment in a photolithographic design. The edge fragment has a tag classification that defines a contrast of the edge fragment. The contrast-based RET applies a resolution enhancement to the edge fragment based on the tag classification. The resolution enhancement introduces an additional feature in the photolithographic design. The additional feature changes the contrast of the edge fragment.

Abstract: Computer-based design and verification tools provide integrated circuit layouts for use in chromeless phase lithography. A phase-mask design tool assigns feature size descriptors to circuit layout features, and mask features are configured using the feature size descriptors. Feature size descriptors can be assigned based on feature size ranges established based on a mask error function, feature dimensions with respect to a lithographic system resolution limit, or selected properties of aerial image intensity as a function of feature size. Circuit layout features are assigned mask features that include twin phase steps. In addition, circuit layout features associated with selected feature descriptors are assigned sub-resolution assist mask pattern portions or other mask pattern portions based on optical and process corrections.

Abstract: A contrast-base resolution enhancing technology (RET) receives an indication of an edge fragment in a photolithographic design. The edge fragment has a tag classification that defines a contrast of the edge fragment. The contrast-based RET applies a resolution enhancement to the edge fragment based on the tag classification. The resolution enhancement introduces an additional feature in the photolithographic design. The additional feature changes the contrast of the edge fragment.

Abstract: A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and “vertical” critical features from a plurality of features forming a layout; identifying interconnection areas which are areas in which one of the horizontal critical features or the vertical critical features contacts another feature of the layout; defining a set of primary parameters on the basis of the proximity of the plurality of features relative to one another; and generating an edge modification plan for each interconnection area based on the primary parameters. A horizontal mask pattern is then generated by compiling the horizontal critical features, a first shield plan for the vertical critical features and the interconnection areas containing a horizontal critical feature modified by the edge modification plan.

Abstract: A ceramic material for electronic circuit devices is sintered at less than r equal to 1000.degree. C. temperature. A filler material such as quartz and a glassy binder RO-Al.sub.2 O.sub.3 -B.sub.2 O.sub.3 are mixed together along with an appropriate glassy binder prior to firing. RO is drawn from the group of metal oxides MgO, CaO, SrO, BaO, ZnO or CdO and the glassy binders form no more than 40 vol % of the ceramic material. The glassy binder has a suitable viscosity and other properties so that after it is mixed with the quartz filler, sintering occurs at the relatively low temperature. As a consequence, high conductivity conductors made of copper, silver and gold can be appropriately metallized prior to firing. The strength and low dielectric constant of the ceramic material make the material well adapted for ceramic substrates, thick films and the like which are used in VHSIC and VLSI applications.