Patents by Inventor Andreus Wiesner

Andreus Wiesner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100277966
    Abstract: A memory arrangement comprises a first memory transistor (11) for non-volatile storage of a first bit, a second memory transistor (17) for non-volatile storage of the first bit in inverted form, and a word line (29) that is connected to a control terminal (12) of the first memory transistor (11) and a control terminal (18) of the second memory transistor (17). The memory arrangement further comprises a read amplifier (23) with a first input (24) that is coupled to the first memory transistor (11) for supplying a first bit line signal (BL1), a second input (25) that is coupled to the second memory transistor (17) for supplying a second bit line signal (BL2), and an output (26) for provision of an output signal (SOUT) as a function of the first bit line signal (BL1) and the second bit line signal (BL2).
    Type: Application
    Filed: July 2, 2008
    Publication date: November 4, 2010
    Inventors: Gregor Schatzberger, Andreus Wiesner