Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Abstract: Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.

Abstract: In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Abstract: In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Abstract: Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Abstract: A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.

Abstract: Embodiments are directed to a method of mitigating voltage noise events. The method includes detecting the presence of a voltage noise event at the integrated circuit device. Thereafter, one or more local clock buffers (LCBs) is selected for dampening. A type of dampening is selected for the LCBs. Finally, the dampening is applied to the LCB while the voltage noise event is occurring.

Abstract: Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.

Abstract: Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.