Patents by Inventor Andrew A. Wereszczak

Andrew A. Wereszczak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160255747
    Abstract: A number of variations may include a device that may include a first substrate having at least one concentrically ground surface; and a second substrate overlying the first substrate in a hexagonally-arrayed print pattern.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: VICENTIU GROSU, ANDREW A. WERESZCZAK
  • Publication number: 20150232731
    Abstract: A hybrid-filled, electrically insulating composition includes a resinous matrix comprising 56 to 65 volume percent of the total composition and a particulate dispersed phase comprising essentially the balance of the total composition. The dispersed phase includes a first ceramic component such as AlN, BN, or BeO and a second ceramic component such as MgO, Al2O3, SiO2, a polycrystalline alumino-silicate, and/or a metal. The dispersed phase makes up more than 50 volume percent of the first component. The molding composition has a thermal conductivity of at least 3.5 W/mK.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Inventor: Andrew A. Wereszczak
  • Patent number: 8938993
    Abstract: High intensity plasma-arc heat sources, such as a plasma-arc lamp, are used to irradiate glass, glass ceramics and/or ceramic materials to strengthen the glass. The same high intensity plasma-arc heat source may also be used to form a permanent pattern on the glass surface—the pattern being raised above the glass surface and integral with the glass (formed of the same material) by use of, for example, a screen-printed ink composition having been irradiated by the heat source.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: January 27, 2015
    Assignee: UT-Battelle, LLC
    Inventors: David C. Harper, Andrew A. Wereszczak, Chad E. Duty
  • Publication number: 20140255717
    Abstract: Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: UT-BATTELLE, LLC
    Inventor: Andrew A. Wereszczak
  • Patent number: 8822036
    Abstract: Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 2, 2014
    Assignee: UT-Battelle, LLC
    Inventor: Andrew A. Wereszczak
  • Publication number: 20130307200
    Abstract: Methods and processes to fabricate thermoelectric materials and more particularly to methods and processes to fabricate doped silicon-based semiconductive materials to use as thermoelectrics in the production of electricity from recovered waste heat. Silicon metal particulates, extracting liquid, and dopant are combined into a mixture and milled. Substantially oxidant-free and doped silicon metal particulates are recovered and sintered to form a porous polycrystalline silicon-based thermoelectric material.
    Type: Application
    Filed: November 2, 2012
    Publication date: November 21, 2013
    Inventors: John Carberry, Andrew A. Wereszczak
  • Publication number: 20130310487
    Abstract: Thermally conductive, electrically insulating epoxy molding compounds that use milled silicon as a filler material, and methods and processes for making the same. Some example embodiments of the present invention comprise the use of a passivation agent, for example ethyl silicate, to deposit a thin layer of glass on the surfaces of the powders as the powders are milled, creating an attractive surface dielectric property on these surfaces.
    Type: Application
    Filed: November 2, 2012
    Publication date: November 21, 2013
    Applicant: Mossey Creek Solar, LLC
    Inventors: John Carberry, Andrew A. Wereszczak
  • Publication number: 20120131960
    Abstract: High intensity plasma-arc heat sources, such as a plasma-arc lamp, are used to irradiate glass, glass ceramics and/or ceramic materials to strengthen the glass. The same high intensity plasma-arc heat source may also be used to form a permanent pattern on the glass surface—the pattern being raised above the glass surface and integral with the glass (formed of the same material) by use of, for example, a screen-printed ink composition having been irradiated by the heat source.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: David C. Harper, Andrew A. Wereszczak, Chad E. Duty
  • Publication number: 20110297203
    Abstract: Practices are described for preparing fine-grain, stress-tolerant, brittle, doped semiconductor thermoelectric elements better suited to withstand thermal and mechanical loads without cracking or fracture. Preparation entails net shape powder processing of substantially isotropic thermoelectric compounds such as skutterudites under conditions which promote reduction of the largest grain sizes in a grain size distribution. Nearly three-fold improvements in fracture strength over conventionally-processed thermoelectric elements are observed. The net shape powder processing is adapted for the ready incorporation of the net shape thermoelectric elements into a thermoelectric device.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: James R. Salvador, Jihui Yang, Andrew A. Wereszczak
  • Patent number: 7796388
    Abstract: The disclosure describes directly cooling a three-dimensional, direct metallization (DM) layer in a power electronics device. To enable sufficient cooling, coolant flow channels are formed within the ceramic substrate. The direct metallization layer (typically copper) may be bonded to the ceramic substrate, and semiconductor chips (such as IGBT and diodes) may be soldered or sintered onto the direct metallization layer to form a power electronics module. Multiple modules may be attached to cooling headers that provide in-flow and out-flow of coolant through the channels in the ceramic substrate. The modules and cooling header assembly are preferably sized to fit inside the core of a toroidal shaped capacitor.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: September 14, 2010
    Assignee: UT-Battelle, LLC
    Inventors: Randy H. Wiles, Andrew A. Wereszczak, Curtis W. Ayers, Kirk T. Lowe
  • Publication number: 20090231812
    Abstract: The disclosure describes directly cooling a three-dimensional, direct metallization (DM) layer in a power electronics device. To enable sufficient cooling, coolant flow channels are formed within the ceramic substrate. The direct metallization layer (typically copper) may be bonded to the ceramic substrate, and semiconductor chips (such as IGBT and diodes) may be soldered or sintered onto the direct metallization layer to form a power electronics module. Multiple modules may be attached to cooling headers that provide in-flow and out-flow of coolant through the channels in the ceramic substrate. The modules and cooling header assembly are preferably sized to fit inside the core of a toroidal shaped capacitor.
    Type: Application
    Filed: March 9, 2009
    Publication date: September 17, 2009
    Inventors: Randy H. Wiles, Andrew A. Wereszczak, Curtis W. Ayers, Kirk T. Lowe