Abstract: A load/store pipeline uses a store buffer pipeline to avoid data dependency issues and resource conflicts. Store instructions are stored in the store buffer pipeline. During processing of a later store instruction, the stored instruction stores data into the memory system. Specifically the stored store instruction stores data during the same load/store pipeline stage that a load instruction would read data from the memory system. Thus, memory resource conflicts caused by a store instruction followed by a load instruction are avoided. Some embodiments of the present invention includes N store buffer stages so that a first store instruction is not carried out until the (N+1)th store instruction is processed. The delay provided by the store buffer pipeline can be used to process information regarding the store instruction such as cache hits or misses and store cancellation instructions.