Abstract: A method of providing a deterministic microcontroller includes a providing a plurality of blocks of cache memories formed on the same integrated circuit as a microprocessor unit.

Abstract: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided. The deterministic microcontroller includes a configurable input/output interface that is programmable to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A deterministic microcontroller includes a plurality of blocks of cache memories formed on the same integrated circuit as the microprocessor unit.

Abstract: A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers.

Abstract: Disclosed is system and method for managing a multiprocessor system including at least one master processor in communication with at least one remote processor. A core interacts with one or more distributed processors through communication channels. The core provides test, synchronization, logging, and management operations to distributed processors. An agent engine, associated with the core, provides operation-related data and software from a combination of user interfaces, test scripts, and databases to the core during its interaction with the distributed processors. Target agents associated with the distributed processors receive commands from the core. Target agents can access library modules for extended command sets for target processor management, testing, and control. Target agent capability can be extended via on-line or real-time task distribution.