Abstract: An autonomous vehicle includes a chassis for housing an aircraft ground contacting structure (GCS) and one or more GCS coupling and lifting mechanisms, GCS securing mechanisms, drivetrain, batteries and a sensor stack for performing autonomous navigation. Further, the vehicle incorporates multiple sensors, such as high-resolution machine vision cameras, GPS modules, Lidars, ultrasonic range sensors, and radars. The sensors deliver spatial perception capabilities to the vehicle and feed relevant data to onboard computing units to achieve location-based navigation, precision alignment with aircraft, obstacle detection and collision avoidance capabilities. A series of batteries deliver power to all components, including but not limited to, motors, electromechanical units, onboard computers, sensors and any other component requiring electrical input. External ports allow the vehicle to recharge batteries after each utilization cycle without replacement.

Abstract: An integrated circuit structure includes a fin or a plurality of horizontally stacked nanowires above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the fin or the plurality of horizontally stacked nanowires and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin or the plurality of horizontally stacked nanowires, the dielectric gate plug including a dielectric liner including silicon and oxygen, and a dielectric fill including silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Abstract: Integrated circuit (IC) device isolation structures between transistor gates. An IC device may include an electrically insulating structure between metal gates of adjacent transistors, and the insulating structure may include a dielectric liner around a different dielectric fill material and on sidewalls of the adjacent metal gates. The dielectric liner may be much thinner than the dielectric fill material. A metal via may be through, and in contact with, the dielectric fill material. The adjacent transistors and metal gates may be between frontside and backside interconnect structures, and the metal via may extend between, and couple, the interconnect structures.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. Some of the gate cuts may be at least 2× wider than others. Such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. Conductive contacts formed over the source and drain regions along a source/drain trench. The gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. The contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. Accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

Abstract: An apparatus for securing to an outer surface of a segment of flexible pipe body, comprising an outer clamp portion around a region of flexible pipe body and comprising a plurality of outer body members each having an inner surface; and an inner clamp portion in an abutting relationship between the outer clamp portion and said flexible pipe body, comprising a plurality of inner body members each having an outer surface that comprises a mating region that has a shape that mates with a shape of a corresponding mating region of the inner surface of the outer clamp portion. Each mating region comprises at least one clamping surface region that in an imaginary plane that extends through and includes a primary axis of the pipe body, arranged oblique to the primary axis when the inner clamp portion is between the outer clamp portion and the pipe body.

Abstract: An autonomous vehicle includes a chassis for housing an aircraft ground contacting structure (GCS) and one or more GCS coupling and lifting mechanisms, GCS securing mechanisms, drivetrain, batteries and a sensor stack for performing autonomous navigation. Further, the vehicle incorporates multiple sensors, such as high-resolution machine vision cameras, GPS modules, Lidars, ultrasonic range sensors, and radars. The sensors deliver spatial perception capabilities to the vehicle and feed relevant data to onboard computing units to achieve location-based navigation, precision alignment with aircraft, obstacle detection and collision avoidance capabilities. A series of batteries deliver power to all components, including but not limited to, motors, electromechanical units, onboard computers, sensors and any other component requiring electrical input. External ports allow the vehicle to recharge batteries after each utilization cycle without replacement.

Abstract: An automated system and method provides for planning and response to disparate threats with combined kinetic (e.g., missile interceptor) and non-kinetic (e.g., cyber and electronic warfare) effects. The threat and effects inputs and the results of analysis tools that individually apply a single effect type to negate a threat vulnerability are normalized to a form and format ingestible by a Stochastic Math Model (SMM). The normalized inputs reflect the success/failure of the effect versus a threat vulnerability as a score, not a probability. The normalized results decompose a probability of defeat (Pdefeat) for an individual effect as a set of hierarchical parameters represented as probabilities.

Abstract: An automated system and method provides for planning and response to disparate threats with combined kinetic (e.g., missile interceptor) and non-kinetic (e.g., cyber and electronic warfare) effects. The threat and effects inputs and the results of analysis tools that individually apply a single effect type to negate a threat vulnerability are normalized to a form and format ingestible by a Stochastic Math Model (SMM). The normalized inputs reflect the success/failure of the effect versus a threat vulnerability as a score, not a probability. The normalized results decompose a probability of defeat (Pdefeat) for an individual effect as a set of hierarchical parameters represented as probabilities.

Abstract: A method for unsupervised anomaly detection, which are algorithms that are designed to process unlabeled data. Data elements are mapped to a feature space which is typically a vector space d. Anomalies are detected by determining which points lies in sparse regions of the feature space. Two feature maps are used for mapping data elements to a feature apace. A first map is a data-dependent normalization feature map which we apply to network connections. A second feature map is a spectrum kernel which we apply to system call traces.

Abstract: A method for unsupervised anomaly detection, which are algorithms that are designed to process unlabeled data. Data elements are mapped to a feature space which is typically a vector space d. Anomalies are detected by determining which points lies in sparse regions of the feature space. Two feature maps are used for mapping data elements to a feature apace. A first map is a data-dependent normalization feature map which we apply to network connections. A second feature map is a spectrum kernel which we apply to system call traces.

Abstract: An electroluminescent display includes a display substrate, a plurality of patterned first electrodes formed over the display substrate, one or more layers of light-emitting material formed over the plurality of first electrodes, at least one second electrode formed over the one or more layers of light-emitting material, and a plurality of chiplets. Each chiplet is electrically connected to a first electrode. Each chiplet further includes a light detector and a light emitter separate from the one-or-more layers of light-emitting material connected to the chiplet circuitry. The chiplet circuitry includes a modulating circuit for modulating light emitted by the light emitter and a demodulating circuit for demodulating light detected by the light detector so that light emitted by the light emitter of a first chiplet is received by the light detector of a second chiplet.

Abstract: An apparatus for displaying and sensing images includes a display substrate and a plurality of electroluminescent pixels. A plurality of pixel control chiplets and one or more sensor chiplets are affixed to the device side of the display substrate in the display area. A transparent cover is spaced apart from and affixed to the device side of the display substrate, and has a plurality of imaging lenses formed on or in it, each imaging lens spaced apart from and corresponding to an image sensor array in a sensor chiplet for forming an imaging plane on the corresponding image sensor array.

Abstract: An apparatus for displaying and sensing images includes a display substrate and a plurality of electroluminescent pixels. A plurality of pixel control chiplets and one or more sensor chiplets are affixed to the device side of the display substrate in the display area. A transparent cover is spaced apart from and affixed to the device side of the display substrate, and has a plurality of imaging lenses formed on or in it, each imaging lens spaced apart from and corresponding to an image sensor array in a sensor chiplet for forming an imaging plane on the corresponding image sensor array.

Abstract: An electroluminescent display includes a display substrate, a plurality of patterned first electrodes formed over the display substrate, one or more layers of light-emitting material formed over the plurality of first electrodes, at least one second electrode formed over the one or more layers of light-emitting material, and a plurality of chiplets. Each chiplet is electrically connected to a first electrode. Each chiplet further includes a light detector and a light emitter separate from the one-or-more layers of light-emitting material connected to the chiplet circuitry. The chiplet circuitry includes a modulating circuit for modulating light emitted by the light emitter and a demodulating circuit for demodulating light detected by the light detector so that light emitted by the light emitter of a first chiplet is received by the light detector of a second chiplet.

Abstract: A building information management (BIM) system is provided with a library platform that supports a toolset with novel functionality. Embodiments of the invention provide a library of products that can be used in a BIM and provide a virtual product set with improved functionality and more detailed information about the products. The library of products includes virtual products that comprise parametrically described data objects. The toolset includes an editor with which the virtual products can be edited and modified. The library of virtual products can be configured for interoperability with multiple BIM systems.

Abstract: A top-emitting OLED device, comprising: one or more OLEDs formed on a substrate; a light-scattering layer formed over the one or more OLEDs; a transparent cover; one or more color filters formed on the transparent cover; a color-conversion material layer formed over the color filters, or formed over or integral with the light-scattering layer; wherein the substrate is aligned and affixed to the transparent cover so that the locations of the color filters and color conversion material correspond to the location of the OLEDs, and the color-conversion material layer, color filters, and the light-scattering layer are between the cover and substrate, and a low-index gap is formed between the light-scattering layer and the color filters, with no light-scattering layer being positioned between the color conversion material layer and the low-index gap.

Abstract: An improved OLED color display device is disclosed, in which a display pixel has a plurality of light-emitting elements of different colors, wherein the areas of the light-emitting elements are different based on the emission efficiency of the light-emitting elements and the luminance stability over time of the light-emitting elements, thereby protecting the light-emitting elements whose emission efficiency or luminance stability is low from prematurely deteriorating, wherein the improvement comprises: the relative areas of the light-emitting elements being further based on a display usage profile including probabilities of different colors to be produced on the display during its lifetime, thereby further extending the useful lifetime of the display.