Abstract: A certain type of gates, such as NOT gates, in a logic network are moved to the network boundary (i.e., inputs or outputs), at least in part, by selecting nodes in the network as candidate nodes for choosing among to determine output phase assignments. Such a candidate node is selected in response to non-reconvergence of branches fanning out from the node.

Abstract: At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.

Abstract: A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.

Abstract: In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

Abstract: A method and implementing structure for a domino block circuit 200 includes a minimal component latching circuit 203 which is merged with an exemplary MUX functional block 201, to provide both inverting and latching functions with minimal propagation delay in the domino data path. Implementations with scanning circuitry and including a holding feature are also illustrated.

Abstract: A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields.