Abstract: A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.

Abstract: A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.

Abstract: A cache on-demand module employing a cache performance module for managing size adjustments to an active cache size of a cache memory in view of supporting an optimal performance of a storage subsystem employing the cache memory by determining an optimal active cache size of the cache memory for supporting the optimal performance of the storage subsystem, and reporting any size adjustment to the active cache size of the cache memory based on the determined optimal active cache size of the cache memory. The cache on-demand module further employs a cache accounting module for managing a client expense account associated with the cache memory by determining whether a client charge or a client rebate is warranted as a function of any size adjustment to the active cache size of the cache memory by the cache performance module.

Abstract: Aspects of increasing the quality and reliability of desktop class storage disks in enterprise storage applications are described. The aspects include monitoring a number of idle states and busy states in a disk drive, and limiting performance of read/write commands by the disk drive based on whether a sufficient number of idle states has been monitored to avoid exceeding a duty cycle rating of the disk drive.

Abstract: The peripheral bus connector for improved aggregation of resources of a device on the peripheral bus includes a plurality of aggregation pins, in addition to the pins according to the peripheral bus standard. Signals from a controller on an extended peripheral bus adapter sends and receives signals in addition to standard signals of the peripheral bus through the aggregation pins. The aggregated device is hidden from third parties, and its existence is known only to the controller on the extended peripheral bus adapter. In this manner, resources are aggregated across a peripheral bus without needing the addition of another controller and without the need to redefine standard peripheral bus signals. In addition, standard peripheral bus adapters may still be used in the connector if resource aggregation is not desired.

Abstract: The peripheral bus connector for improved aggregation of resources of a device on the peripheral bus includes a plurality of aggregation pins, in addition to the pins according to the peripheral bus standard. Signals from a controller on an extended peripheral bus adapter sends and receives signals in addition to standard signals of the peripheral bus through the aggregation pins. The aggregated device is hidden from third parties, and its existence is known only to the controller on the extended peripheral bus adapter. In this manner, resources are aggregated across a peripheral bus without needing the addition of another controller and without the need to redefine standard peripheral bus signals. In addition, standard peripheral bus adapters may still be used in the connector if resource aggregation is not desired.

Abstract: A method and system for mapping a node topology is disclosed. The node topology is based on a computer system comprised of a high performance acyclic serial bus and a plurality of nodes coupled to the acyclic serial bus. Each node further includes an identification packet. The mapping topology establishes a root node based upon information found in each identification packet and establishes at least one branch node among the nodes based on the information. Next, the topology mapping method selects a first available branch node among the available branch nodes based on the information. The system then identifies any of the nodes that are child nodes to the first available branch node. Upon identifying all child nodes of the branch node, the system selects a next available branch node based upon the information. The processing continues until the root node is processed as a branch node.

Abstract: A method and system for determining the maximum number of cable segments between all possible node to node paths on a high performance serial bus. The method for determining the maximum cable hops on the serial bus, which is acyclic and based upon the IEEE 1994 standard, consists of traversing a direct path between two nodes via the parent links. Further, the number of traversed paths is reduced from all possible node-to-node paths to only leaf-to-leaf node paths and leaf-to-root node paths for efficiently identifying the maximum number of cable segments between any two nodes within the serial bus.

Abstract: Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer).

Abstract: In a tree topology network, a method for determining the maximum transfer speed for data packets transmitted over a high performance acyclic serial bus is disclosed. The acyclic serial bus, patterned along the lines of the IEEE 1394 standard, is capable of operating at multiple transmission rates, depending upon the transmission rate of any particular node. Once the transfer speeds have been determined by finding transmission rates to and from an ancestor node, an efficient storage technique for representing the transfer speeds is also disclosed. The method supports packet speed selection for all types of data packets allowed by the IEEE standard, such as, for example, asynchronous, isochronous and broadcast packets.

Abstract: A SCSI computer system is provided whereby a host computer gains access to a targeted but non-local peripheral device, which device or devices are individually responsive to either SCSI or non-SCSI commands, by sending SCSI commands via a SCSI bus to a connected SCSI target computer which emulates the targeted peripheral device local to the SCSI target computer, whether the targeted peripheral device is responsive to only SCSI or only non-SCSI commands, to cause the targeted peripheral device to carry out the initial SCSI commands.

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

Abstract: Apparatus for assigning addresses to devices connected to a small computer system interface (SCSI) bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Abstract: A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Abstract: A plug-in feature board for a computer system has special circuitry to permit the board to customize itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector configurations presented in respective slots.

Abstract: On board diagnostic capability for a SCSI controller is provided within an adapter by providing a gate array driven by a microprocessor on board the adapter. The gate array has data and control inputs driven from the microprocessor and data and control outputs which are dot OR'ed with corresponding in/out terminals of the SCSI controller. A reset signal from a SCSI bus forms a further input to the gate array. For testing purposes the microprocessor drives the gate array inputs to simulate a fault-free or faulty device. The microprocessor detects the response of the SCSI controller to the device simulation and thereby can determine the state of health of the SCSI controller.

Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device into a personnal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, a protection means and at least one direct access storage device. The read only memory includes a first portion of BIOS and data representing the type of system processor and system planar I/O configuration. The first portion of BIOS initializes the system and the direct access storage device, and resets the protection means in order to read in a master boot record into the random access memory from a protectable partition on the direct access storage device.

Abstract: A Graphic Development Instrument System (GDIS) provides a method and capability to design, create and update display screens, including static elements (never change) and dynamic elements (change responsive to stimuli) and is able to include any controller function, without rewriting or modifyng the software. The GDIS enables a screen designer to create EPROMS for those screens for different for example vehicles or models.

Abstract: An advanced display system controller is described for use in automotive vehicles. The controller has electronic circuitry to allow it to be programmed to display monochrome or color graphics and text on an all-points-addressable display device such as a CRT or an Electro-Luminescent (EL) Flat panel. The display resolution and scan rates may be programmed differently depending on the display type and size. The vehicle operator controls the display system via a reconfigurable switch system (RSS), such as an Infrared Touch Panel or Mylar Touch Switch Matrix mounted over the face of the display. In addition, external discrete switches may also be attached to the controller. The controller includes a master microprocessor and a slave microprocessor with preferred partitioning of functions and communicates with other parts of the vehicle via two serial data communication links, a Random Access bus and a Poll/Response bus.