Abstract: A system and method for determining the positioning of mobile-appliance location determining sensors in a mobile-appliance communications network by estimating the positioning accuracy of the sensors.

Abstract: A system and method for determining the positioning of mobile-appliance location determining sensors in a mobile-appliance communications network by estimating the positioning accuracy of the sensors.

Abstract: A system and method for determining the location of a mobile appliance where the tasking of the system to determine the location of the mobile appliance utilizes a first communications protocol standard and the reporting of the location of the mobile appliance utilizes a second communications protocol standard, where the first and second communication protocol standards are not the same and can include any of the commonly used communication protocol standards including TIA defined standards, ETSI standards, and SMR/ESMR defined standards.

Abstract: A spark plug tube removal tool includes a cylindrical body member and an attached wedge member which may be driven by a bolt against the body member to alter the effective diameter of the tool upon insertion into a spark plug tube so as to wedge the tool within the tube and permit removal of the tube from an engine by turning or working the tool engine block.

Abstract: A furnace heat exchanger with multiple parallel flow passages with at least two of the passages being partially formed of a pair of opposed sidewalls having wavy cross-sectional shapes wherein the downstream passage has at least as many and preferably more waves than the upstream pass. The wavy shapes are preferably generally sinusoidal in form with the waves of the two sides being substantially in phase.

Abstract: A system and method for determining the positioning of mobile-appliance location determining sensors in a mobile-appliance communications network by estimating the positioning accuracy of the sensors.

Abstract: For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

Abstract: A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.

Abstract: An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.

Abstract: An information handling system includes a data comparison circuit which includes a number of multi-bit comparison circuit modules, wherein each of the multi-bit comparison circuit modules includes a circuit for comparing two or more bits from a first data source with two or more bits from a second data source to produce an output indicating that the data bits from the first data source are equal to the data bits from the second data source; one or more AND gates for ANDing output signals from each of the first set of circuit modules to produce an output signal if all bits in the first data source are equal to all bits in a second data source; one or more second circuit modules for providing an output signal indicating that data bits from the first data source are unequal to corresponding data bits from the second data source; and one or more inequality combination circuits combining inequality signals from each of the second set of circuit modules to produce an output when value of data from the first data so

Abstract: A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.